NeurIPS 2019
Sun Dec 8th through Sat the 14th, 2019 at Vancouver Convention Center
Paper ID:1093
Title:Channel Gating Neural Networks

The paper presents a simple yet effective way to reduce computation by only computing a sub-part of the inner-products. This idea results in realization speedups as confirmed by an ASIC design. Given the similarity with some existing work on dynamic pruning, I recommend acceptance as a poster.