{"title": "Analog Soft-Pattern-Matching Classifier using Floating-Gate MOS Technology", "book": "Advances in Neural Information Processing Systems", "page_first": 1131, "page_last": 1138, "abstract": null, "full_text": "Analog Soft-Pattern-Matching Classifier \n\nusing Floating-Gate MOS Technology \n\n \n\n \n\nToshihiko YAMASAKI and Tadashi SHIBATA* \n\nDepartment of Electronic Engineering, School of Engineering \n*Department of Frontier Informatics, School of Frontier Science \n\nThe University of Tokyo \n\n7-3-1 Hongo, Bunkyo-ku, Tokyo, 113-8656, Japan \n\nyamasaki@if.t.u-tokyo.ac.jp, shibata@ee.t.u-tokyo.ac.jp \n\nAbstract \n\nA flexible pattern-matching analog classifier is presented in con-\njunction with a robust image representation algorithm called Prin-\ncipal Axes Projection (PAP). In the circuit, the functional form of \nmatching is configurable in terms of the peak position, the peak height \nand the sharpness of the similarity evaluation. The test chip was fabri-\ncated in a 0.6-m m CMOS technology and successfully applied to \nhand-written pattern recognition and medical radiograph analysis using \nPAP as a feature extraction pre-processing step for robust image coding. \nThe separation and classification of overlapping patterns is also ex-\nperimentally demonstrated. \n\n1 Introduction \n\nPattern classification using template matching techniques is a powerful tool in im-\nplementing human-like intelligent systems. However, the processing is computa-\ntionally very expensive, consuming a lot of CPU time when implemented as soft-\nware running on general-purpose computers. Therefore, software approaches are not \npractical for real-time applications. For systems working in mobile environment, in \nparticular, they are not realistic because the memory and computational resources \nare severely limited. The development of analog VLSI chips having a fully parallel \ntemplate matching architecture [1,2] would be a promising solution in such applica-\ntions because they offer an opportunity of low-power operation as well as very \ncompact implementation. \n\nIn order to build a real human-like intelligent system, however, not only the pattern \nrepresentation algorithm but also the matching hardware itself needs to be made \nflexible and robust in carrying out the pattern matching task. First of all, \ntwo-dimensional patterns need to be represented by feature vectors having substan-\ntially reduced dimensions, while at the same time preserving the human perception \nof similarity among patterns in the vector space mapping. For this purpose, an im-\nage representation algorithm called Principal Axes Projection (PAP) has been de-\n\n\f \n\nveloped [3] and its robust nature in pattern recognition has been demonstrated in the \napplications to medical radiograph analysis [3] and hand-written digits recognition \n[4]. However, the demonstration so far was only carried out by computer simulation. \n\nRegarding the matching hardware, high-flexibility analog template matching circuits \nhave been developed for PAP vector representation. The circuits are flexible in a \nsense that the matching criteria (the weight to elements, the strictness in matching) \nare configurable. In Ref. [5], the fundamental characteristics of the building block \ncircuits were presented, and their application to simple hand-written digits was pre-\nsented in Ref. [6]. The purpose of this paper is to demonstrate the robust nature of \nthe hardware matching system by experiments. The classification of simple \nhand-written patterns and the cephalometric landmark identification in gray-scale \nmedical radiographs have been carried out and successful results are presented. In \naddition, multiple overlapping patterns can be separated without utilizing a priori \nknowledge, which is one of the most difficult problems at present in artificial intel-\nligence. \n\n2 Image representation by PAP \n\nPAP is a feature extraction technique using the edge information. The input image \n(64x64 pixels) is first subjected to pixel-by-pixel spatial filtering operations to de-\ntect edges in four directions: horizontal (HR); vertical (VR); +45 degrees (+45); and \n\u201345 degrees (-45). Each detected edge is represented by a binary flag and four edge \nmaps are generated. The two-dimensional bit array in an edge map is reduced to a \none-dimensional array of numerals by projection. The horizontal edge flags are ac-\ncumulated in the horizontal direction and projected onto vertical axis. The vertical, \n+45-degree and \u201345-degree edge flags are similarly projected onto horizontal, \n-45-degree and +45-degree axes, respectively. Therefore the method is called \u201cPrin-\ncipal Axes Projection (PAP)\u201d [3,4]. Then each projection data set is series connected \nin the order of HR, +45, VR, -45 to form a feature vector. Neighboring four ele-\nments are averaged and merged to one element and a 64-dimensional vector is fi-\nnally obtained. This vector representation very well preserves the human perception \nof similarity in the vector space. In the experiments below, we have further reduced \nthe feature vector to 16 dimensions by merging each set of four neighboring ele-\nments into one, without any significant degradation in performance. \n\n3 Circuit configurations \n\nA B\n\nC\n\nVGG\n\nIOUT\n\nA B\n\nC\n\nVGG\n\nIOUT\n\nVIN\n\n1\n\n2\n\n4\n\n1\n\nRST\n\n\u0002\u0001\u0004\u0003\n\nVIN\n\n1\n\n2\n\n4\n\n13\n\nRST\n\n\u0006\u0005\u0007\u0003\n\n \n\nFigure 1: Schematic of vector element matching circuit: (a) pyramid (gain re-\nduction) type; (b) plateau (feedback) type. The capacitor area ratio is indicated \nin the figure. \n\n\f \n\nThe basic functional form of the similarity evaluation is generated by the shortcut \ncurrent flowing in a CMOS inverter as in Refs. [7,8,9]. However, their circuits were \nutilized to form radial basis functions and only the peak position was programmable. \nIn our circuits, not only the peak position but also the peak height and the sharpness \nof the peak response shape are made configurable to realize flexible matching op-\nerations [5]. \n\nTwo types of the element matching circuit are shown in Fig. 1. They evaluate the \nsimilarity between two vector elements. The result of the evaluation is given as an \noutput current (IOUT) from the pMOS current mirror. The peak position is temporar-\nily memorized by auto-zeroing of the CMOS inverter. The common-gate transistor \nwith VGG stabilizes the voltage supply to the inverter. By controlling the gate bias \nVGG, the peak height can be changed. This corresponds to multiplying a weight fac-\ntor to the element. The sharpness of the functional form is taken as the strictness of \nthe similarity evaluation. In the pyramid type circuit (Fig. 1(a)), the sharpness is \ncontrolled by the gain reduction in the input. In the plateau type (Fig. 1(b)), the \noutput voltage of the inverter is fed back to input nodes and the sharpness changes \nin accordance with the amount of the feedback. \n\n\u0016! \u0006\u0016\u0004\"!\u0016\n\n\u0012\u0014\u0013\u0015\u0013\u0015\u0016\n\n\u0012\u0014\u001d\n\n\u001e\u0015\u0016\n\n\f\u001f\b\n\n\u0018\u0015\u0019\u001b\u001a\u001c\u0016\n\n\u0012\u0014\u001d\n\n\u0018\u001b\u0019\u0015\u001a\n\n\u0018\u0015\u0019\u0015\u001a\u001c'\n\n\u0007\t\b\n\u0003\u0006\u000b\n\n#$ %#&\"\u0014#\n\n\u0012\u0014\u0013\u0015\u0013\u001c#\n\n'( \u001f')\"\u000f'\n\n\u0012\u0006\u0013\n\u0013\u0015'\n\n\f\u001f\b\n\n\u0012\u001f\u001d\n\n\u001e\n'\n\n\f\u0014\b\n\n\u0002\u0001\u0004\u0003\u0006\u0005\n\n\r\f\u000f\u000e\u000f\u000b\u0011\u0010\n\n \n\nFigure 2: Schematic of n-dimensional vector matching circuit utilizing the \npyramid type vector element circuits. \n\nl\nl\n\n16-dimension(cid:13)\n15-vector(cid:13)\nmatching circuit\n\nDecoder\n\n4.5mm\n\nA\n-\ne\nk\na\nT\n-\nr\ne\nn\nn\nW\nn\n\ni\n\n \n\ni\na\nm\no\nd\n-\ne\nm\nT\n\ni\n\n \n\nFigure 3: Photomicrograph of \nsoft-pattern-matching classifier\ncircuit. \n\nThe total matching score between input and template vectors is obtained by taking \nthe wired sum of all IOUT\u2019s from the element matching circuits as shown in Fig. 2. A \nmultiplier circuit as utilized in Ref. [8] was eliminated because the radial basis func-\ntion is not suitable for the template matching using PAP vectors. ISUM, the sum of \nIOUT\u2019s, is then sunk through the nMOS with the VRAMP input. This forms a current \ncomparator circuit, which compares ISUM and the sink current in the nMOS with \nVRAMP. The VOUT nodes are connected to a time-domain Winner-Take-All circuit [9]. \nA common ramp down voltage is applied to the VRAMP nodes of all vector matching \ncircuits. When VRAMP is ramped down from VDD to 0V, the vector matching circuit \nyielding the maximum ISUM firstly upsets and its output voltage (VOUT) shows a \n0-to-1 transition. The time-domain WTA circuit senses the first upsetting signal and \nmemorizes the location in the open-loop OR-tree architecture [10]. In this manner, \nthe maximum-likelihood template vector is easily identified. \n\n\u0017\n\u0005\n\u000e\n\u0017\n#\n\u001e\n#\n\u0005\n\u000e\n\u0017\n\u0005\n\u000e\n\f \n\nThe circuits were designed and fabricated in a 0.6-m m double-poly triple-metal \nCMOS technology. Fig. 3 shows the photomicrograph of a pattern classifier circuit \nfor 16-dimensional vectors. It contains 15 vector matching circuits. One element \nmatching circuit occupies the area of 150m m x 110m m. In the latest design, however, \nthe area is reduced to 54 m m x 68 m m in the same technology by layout optimization. \nFurther area reduction is anticipated by employing high-K dielectric films for ca-\npacitors since the capacitors occupy a large area. The full functioning of the chip \nwas experimentally confirmed [6]. In the following experiments, the simple vector \nmatching circuit in Fig. 2 was utilized to investigate the response from each tem-\nplate vector instead of just detecting the winner using the full chip. \n\n4 Experimental results and discussion \n\n4 . 1 V e c t o r- e l e m en t m a t c hi ng c i r c ui t \n\u0018\n\u000b\"\u000b\n\u0018\u0003\u000b\n\u001em\u001f\n\n\u0002\u0001\u0003\u0001\u0003\u0004\u0006\u0005\b\u0007\n\n-1.\n&\u0006'\u0006(\n\n\u0019\u0017\u000b\n\u0018\u0003\t\n\u0018\u0003\u000b\n\n\u001em\u001f\n\n\t\n\n\n\u000b\n\n\t\n\n\n\u0002\u0001\u0003\u0001\u0003\u0004\u0006\u0005\b\u0007\n\u0002\u0001\u0003\u0001\u0003\u0004\u0006\f\b\u0007\n\u0019\b\u0007\n\n\u0002\u0001\u0003\u0001\u0003\u0004\u0006\u0005\b\u0007\n\n\t\n\n\n\u000b\n\n\t\n\n\n\u0002\u0001\u0003\u0001\u0003\u0004\u0006\u0005\b\u0007\n\u0002\u0001\u0003\u0001\u0003\u0004\u0006\f\b\u0007\n\u0019\b\u0007\n\n\u0019\u0017\u000b\n\u0018\u0003\t\n\u0018\u0003\u000b\n\n\u001em\u001f\n\n\u000b\u0017\u0007\n\n-/.\u000e0\n)\u0006*,+\n\n\u000b\u0017\u0007\n\n\u0018\n\u0007\n\u000e\r\n\u000f\u0011\u0010\n\n\u000e\u0012\n\n\u0018\n\u0007\n\u000e\r\n\u000f\u0011\u0010\n\n\u000e\u0012\n\n\u0018\"\u0007\n\u000e\r\n\u000f\u0003\u0010\n\n\u000e\u0012\n\n\u0002\u0001\u0003\u0001\u0003\u0004\u0006\u0005\b\u0007\n\u0002\u0001\u0003\u0001\u0003\u0004\u0006\u0005\b\u0007\n\u0002\u0001\u0003\u0001\u0003\u0004\u0006\f\b\u0007\n\u0002\u0001\u0003\u0001\u0003\u0004\u0006\f\b\u0007\n\n\t\n\n\u000b\n\n\t\n\n\u000b\n\n\n\u0019\b\u0007\n\n\u0002\u0001\u0003\u0001\u0003\u0004\u0006\u0005\b\u0007\n\u0002\u0001\u0003\u0001\u0003\u0004\u0006\u0005\b\u0007\n\u0002\u0001\u0003\u0001\u0003\u0004\u0006\f\b\u0007\n\u0002\u0001\u0003\u0001\u0003\u0004\u0006\f\b\u0007\n\n\t\n\n\u000b\n\n\t\n\n\u000b\n\n\n\u0018\"\u0007\n\u000e\r\n\u000f\u0003\u0010\n\n\u000e\u0012\n\n\u0019\b\u0007\n\n \n\n\u000b!\u0007\n\n\u000b!\u0007\n\n\u000b!\u0007\n\u000b\u0017\u0007\n\u000b!\u0018\n\n\u0018\n\u000b\"\u000b\n\u0018\u0003\u000b\n\u001em\u001f\n\u000b!\u0007\n\u000b\u0017\u0007\n\u000b!\u0018\n\n\u0013\u0011\u0014\u0016\u0015\n\n\u0013$#%\u0015\n\nFigure 4: Measured characteristics: (a) pyramid type; (b) plateau type. VGG was \nvaried from 3.0V to 4.5V, and control signals A~C from 000 to 111 for sharp-\nness control. \n\nFig. 4 shows the measured characteristics of vector-element matching circuits in \nboth linear and log plots. The peak position was set at 1.05V by auto-zeroing. The \npeak height was altered by VGG. Also, the operation mode was altered from the \nabove-threshold region to the sub-threshold region by VGG. In the plateau type cir-\ncuit (Fig. 4(b)), IOUT becomes constant around the peak position and the flat region \nwidens in proportion to the amount of feedback. This is because the inverter oper-\nates so as to keep the floating gate potential constant in the high-gain region of the \ninverter as in the case of virtual ground of an operational amplifier. \n\n\u000b\n\t\n\u0018\n\t\n\u0019\n\t\n\f\n\u000b\n\t\n\u001a\n\u001b\n\u001c\n\u001d\n \n\u0018\n\u0018\n\u0018\n\u0018\n\u001a\n\u001b\n\u001c\n\u001d\n \n\u000b\n\t\n\u0018\n\t\n\u0019\n\t\n\f\n\u000b\n\t\n\u0018\n\t\n\u0019\n\t\n\f\n\u000b\n\t\n\u001a\n\u001b\n\u001c\n\u001d\n \n\u001a\n\u001b\n\u001c\n\u001d\n \n\u000b\n\t\n\u0018\n\t\n\u0019\n\t\n\f\n&\n&\n(\n(\n)\n)\n+\n+\n0\n\f \n\n4 . 2 M a t c h i ng o f s i m pl e h an d- w ri tt e n pa t t e rn s \n\nFig. 5 demonstrates the matching results for the simple input patterns. 16 templates \nwere stored in the matching circuit and several hand-written pattern vectors were \npresented to the circuit as inputs. A slight difference in the matching score is ob-\nserved between the pyramid type and the plateau type, but the answers are correct \nfor both types. Fig. 6 shows the effect of sharpness variation. As the sharpness gets \nsteeper, all the scores decrease. However, the score ratios between the winner and \nloosers are increased, thus enhancing the winner discrimination margins. The \nmatching results with varying operational regimes of the circuit are given in Fig. 7. \nThe circuit functions properly even in the sub-threshold regime, demonstrating the \nopportunity of extremely low power operation. \n\nPresented(cid:13)\nPatterns\n\nTemplate Patterns\n\nBest(cid:13)\nMatched\n\nTemplate Patterns\n\nBest(cid:13)\nMatched\n\n1 2 3 4 5 6 7 8 9 10 1112 13 14 15 16\n\nTemplate #\n\n1 2 3 4 5 6 7 8 9 10 1112 13 14 15 16\n\nTemplate #\n\nFigure 5: Result of simple pattern matching: (a) pyramid type (left) where gain \nreduction level was set with ABC=010; (b) plateau type (right) where feedback \nratio was set with ABC=101. \n\n$\u0012$\n\n\u0017m\u0018\n\n\u0002\u0001\u0004\u0003\u0006\u0005\u0007\u0003\t\b\u000b\n\f\u0003\u0006\r\u000e\u0010\u000f\u0011\n\u0012\n\f\u0003\u0006\u0001\u0006\b\n\n$\f'\n$\f'\n$\f'\n$\f'\n\n,.-0/\u000210243450647\u0011,\n=?>\u0007@\n\n:<;\n\n8\f,\n;\tC\n\n-9,\n\n/9,\n\n19,\n\n29,\n\n,D-0/\u000214203454647E,\n=\u000b>\u0007@\n\n:\u0007;\n\n8\u0012,\n;\tC\n\n-9,\n\n/\u0012,\n\n19,\n\n29,\n\nFigure 6: Effect of sharpness variation in the pyramid type with ABC=010. \n\nInput Pattern\n\nTemplate #4\n\nVGG=4.0V\nVGG=3.5V\nVGG=3.0V\n\nVGG=2.5V\n\n1 2 3 4 5 6 7 8 9 10111213141516\n\nTemplate#\n\n(cid:13)\n\nBest Matched\n\n \n\n \n\n \n\nFigure 7: Matching results as a function of VGG. Correct results are obtained in \nthe sub-threshold regime as well as in the above-threshold regime (the pyramid \ntype was utilized). \n\n4 . 3 A p pl i c a ti o n t o g ra y -s ca l e m e di ca l r a di o g ra p h a n a l y s i s \n\nIn Fig. 8, are presented the result of cephalometric landmark identification experi-\nments, where the Sella (pituitary gland) pattern search was carried out using the \nsame matching circuit. Since the 64-dimension PAP representation is essential for \ngrayscale image recognition, the 64-dimension vector was divided into four \n\n\u0013\n\u0014\n\u0015\n\u0016\n\u0019\n\u0013\n\u0014\n\u0015\n\u0016\n\u0017\n\u001a\n\u001b\n\u001c\n\u001d\n\u001e\n\u001f\n \n!\n\"\n#\n\u0019\n$\n%\n$\n&\n&\n%\n$\n$\n(\n)\n*\n+\n&\n,\n,\n3\nA\nB\n,\n,\n3\nA\nB\n\f \n\n16-dimension vectors and the matching scores were measured separately and then \nsummed up by off-chip calculation. The correct position was successfully identified \nboth in the above-threshold (Fig. 8(b)) and the sub-threshold (Fig. 8(c)) regimes \nusing the 14 learned vectors as templates. In the previous work [3], successful \nsearch was demonstrated by the computer simulation. \n\n \n\n\t\u000b\n\r\f\u0010\f\u000e\u000f\n\n\u0011\u0013\u0012\n\n\u0016\u0018\u0017\n\n\u0019\u001b\u001a\u001d\u001c\u0018\u0015\n\n\u001e\u0002\u001f\n! m\"$#\n\n\u0011\u0013\u0012\n\n\u0016\u0018\u0017\n\n\u0019\u001b\u001a\u001d\u001c\u0018\u0015\n\n\u001e\u0002\u001f\n! m\"$#\n\n\u0002\u0001\u0004\u0003\n\n\t\u000b\n\r\f\u000e\f\u0010\u000f\n\n%'&)(+*-,/.\u000e*\n0\u000e1-2\n<8=\u0006>@?BA\u0004C9DFE\n\u0005\u0006\u0003\n\n3\u0004*+:\n\n3-4658792\nD mG\n\n\t\u000b\n\r\f\u000e\f\u0010\u000f\n\n3\u0004*+:\n\n0\u000e1-2\n%'&)(+*-,/.\u000e*\n3-4658792\nI mG\n<8=\u0006>@?HD\u0004DFE\n\u0002\u0007\b\u0003\n\n \n\nFigure 8: Matching results of Sella search using pyramid type with ABC=000: \n(a) input image; (b) above-threshold regime; (c) sub-threshold regime. \n\n4 . 4 S ep a ra t i o n o f o v e r l a pp i ng pa t t e r ns \n\nSuppose an unknown pattern is presented to the matching circuit. The pattern might \nconsist of a single or multiple overlapping patterns. Let X represent the input vector \nand W1st the winner (best matched) vector obtained by the matching circuit. Let the \nfirst matching trial be expressed as follows: \n\n1st trial:\n\nX\n\nmatching\n\nW \n1st\n\nThen, the residue vector (X-W1st) is generated. The subtraction is perfomed in the \nvector space. When an element in the residue vector becomes negative, the value is \nset to 0. Such operation is easily implemented using the floating gate technique. \nHere, the residue was obtained by off-line calculation. If the input pattern is single, \nthe residue vector is meaningless: only the leftover edge information remains in the \nresidue vector. If the input consists of overlapping patterns, the edge information of \nother patterns remains. If the residue vector is very small, we can expect that the \ninput is single. But in many cases, the residue vector is not so small due to the dis-\ntortion in hand-written patterns. Thus, it is almost impossible to judge which is the \ncase only from the magnitude of the residue vector. Therefore, we proceed to the \nsecond trial to find the second winner: \n\n2nd trial:\n\nX W\n\n1st\n\nmatching\n\nW \n2nd\n\nWith the same sequence, the second residue vector (X-W1st-W2nd), the third \n(X-W1st-W2nd-W3rd) and so forth are generated by repeating the winner subtraction \nafter each trial. Then, new template vectors are generated such as W1st+W2nd, \nW1st+W2nd+W3rd, and so forth. If the input vector is that of a single pattern, the \nmatching score is the highest at W1st and the scores are lower at W1st+W2nd and \nW1st+W2nd+W3rd. On the other hand, if the input vector is that of two overlapping \npatterns, the score is the highest at W1st+W2nd. This procedure can be terminated \nautomatically when the new template composed of n overlapping patterns yields \nlower score than that of n-1 overlapping patterns. In this manner, we are able to \n\n\n\u0014\n\u0015\n \n\u0014\n\u0015\n \n;\n;\n(cid:190)\n(cid:190)\n(cid:190)\n(cid:190)\n\ufb01\n-\n(cid:190)\n(cid:190)\n(cid:190)\n(cid:190)\n\ufb01\n\f \n\nknow how many patterns are overlapping and what patterns are overlapping without \na priori knowledge. An example of separating multiple overlapping patterns is illus-\ntrated in Fig. 9. \n\nPresented Patterns\n\nTemplate Patterns\n\nBest Matched\n\n1st try:\n\n2nd try:\n\n3rd try:\n\nFinal try:\n\n?\n?\n?\n?\n\n+\n\n+\n\n+\n\n+\n\n \n\nFigure 9: Experimental result illustrating the algorithm for separating overlap-\nping patterns. The solid black bars indicate the winner locations. \n\nTemplate Patterns\n\nPresented(cid:13)\nPatterns\n#1\n\n#2\n\n#3\n\nA\n\n+\n\nB\n\nC\n\n(a)\n\n+\n\n+\n\n+\n\n(b)\n\nA\n\nB\n\nC\n\nD\n\nE\n\nF\n\nD\n\nE\n\nF\n\n+\n\n+\n\n+\n\nBest(cid:13)\nMatched\n\n+\n\n+\n\n+\n\n+\n\n+\n\n+\n\n+\n\n \n\nFigure 10: Measured results demonstrating separation of multiple overlapping \npatterns: (a) result of separation and classification (A~F are depicted in (b)); \n(b) newly created templates such as W1st+W2nd, W1st+W2nd+W3rd, and so on. \n\nSeveral other examples are shown in Fig. 10. Pattern #1 is correctly classified as a \nsingle rectangle by yielding the higher score for single template than that for \nW1st+W2nd. Pattern #3 consists of three overlapping patterns, but is erroneously \nrecognized as four overlapping patterns. However, the result is not against human \nperception. When we look at pattern #3, a triangle is visible in the pattern. This \nmistake is quite similar to that made by humans. \n\n \n\n \n\n \n\n \n\n\f \n\n5 Conclusions \n\nA soft-pattern matching circuit has been demonstrated in conjunction with a robust \nimage representation algorithm called PAP. The circuit has been successfully ap-\nplied to hand-written pattern recognition and medical radiograph analysis. The rec-\nognition of overlapping patterns similar to human perception has been also experi-\nmentally demonstrated. \n\nA c k no w l e dg m en t s \n\nTest circuits were fabricated in the VDEC program (The Univ. of Tokyo), in col-\nlaboration with Rohm Corp. and Toppan Printing Corp. The work is partially sup-\nported by the Ministry of Education, Science, Sports and Culture under the \nGrant-in-Aid for Scientific Research (No. 11305024) and by JST in the program of \nCREST. \n\nR e f e re n ce s \n\n[1] G.T. Tuttle, S. Fallahi, and A.A. Abidi. (1993) An 8b CMOS Vector A/D Converter. in \nISSCC Tech. Digest, vol. 36, pp. 38-39. IEEE Press. \n\n[2] G. Cauwenberghs and V. Pedroni. (1995) A Charge-Based CMOS Parallel Analog Vector \nQuantizer. In G. Tesauro, D. S. Touretzky and T.K. Leen (eds.), Advances in Neural In-\nformation Processing Systems 7, pp. 779-786. Cambridge, MA: MIT Press. \n\n[3] M. Yagi, M. Adachi, and T. Shibata. (2000) A Hardware-Friendly Soft-Computing Algo-\nrithm for Image Recognition. X European Signal Processing Conf., Sept. 4-8, 2000 \n(EUSIPCO 2000), Vol. 2, pp. 729-732, Tampere, Finland. \n\n[4] M. Adachi and T. Shibata. (2001) Image Representation Algorithm Featuring Human \nPerception of Similarity for Hardware Recognition Systems. In Proc. of the Int. Conf. on \nArtificial Intelligence (IC-AI'2001), Ed. by H. R. Arabnia, Vol. I, 229-234 (CSREA Press, \nISDBN: 1-892512-78-5), Las Vegas, Nevada, USA, June 25-28, 2001. \n\n[5] T. Yamasaki and T. Shibata. (2001) An Analog Similarity Evaluation Circuit Featuring \nVariable Functional Forms. In Proc. IEEE Int. Symp. Circuits Syst. (ISCAS 2001), Vol. 3, \npp. III-561-564, Sydney, Australia, May. 7-9, 2001. \n\n[6] T. Yamasaki, K. Yamamoto and T. Shibata. (2001) Analog Pattern Classifier with Flexi-\nble Matching Circuitry Based on Principal-Axis-Projection Vector Representation. In Proc. \n27th European Solid-State Circ. Conf. (ESSCIRC 2001), Ed. by F. Dielacher and H. Grun-\nbacher, pp. 212-215 (Frontier Group), Villach, Austria, September 18-20, 2001. \n\n[7] J. Anderson, J. C. Platt, and D. B. Kirk. (1993) An Analog VLSI Chip for Radial Basis \nFunctions. In S. J. Hanson, J. D. Cowan, and C. L. Giles Eds., Advances in Neural Informa-\ntion Processing Systems 5, pp. 765-772., San Maetro, CA; Morgan Kaufmann. \n\n[8] L. Theogarajan and L. A. Akers. (1996) A Multi-Dimentional Analog Gaussian Radial \nBasis Circuit. In Proc. IEEE Int. Symp. Circuits Syst. (ISCAS \u201996), Vol. 3, pp. III-543 -546 \nAtlanta, GA, USA, May, 1996. \n\n[9] L. Theogarajan and L. A. Akers. (1997) A scalable low voltage analog Gaussian radial \nbasis circuit. IEEE Trans. on Circuits and Systems II, Volume 44, No. 11, pp. 977 \u2013979, \n1997. \n\n[10] K. Ito, M. Ogawa and T. Shibata. (2001) A High-Performance Time-Domain Win-\nner-Take-All Circuit Employing OR-Tree Architecture. In Proc. 2001 Int. Conf. on Solid \nState Devices and Materials (SSDM2001), pp. 94-95, Tokyo, Japan, Sep. 26-28, 2001. \n\n\f", "award": [], "sourceid": 2114, "authors": [{"given_name": "Toshihiko", "family_name": "Yamasaki", "institution": null}, {"given_name": "Tadashi", "family_name": "Shibata", "institution": null}]}