{"title": "VLSI Phase Locking Architectures for Feature Linking in Multiple Target Tracking Systems", "book": "Advances in Neural Information Processing Systems", "page_first": 866, "page_last": 873, "abstract": null, "full_text": "VLSI Phase Locking Architectures for \n\nFeature Linking in Multiple Target \n\nTracking Systems \n\nAndreas  G.  Andreou \n\nandreou@jhunix.hcf.jhu.edu \nDepartment of Electrical  and \n\nComputer Engineering \n\nThe Johns  Hopkins  University \n\nBaltimore,  MD  21218 \n\nThomas  G.  Edwards \ntedwards@src.umd.edu \n\nDepartment of Electrical  Engineering \n\nThe University of Maryland \n\nCollege Park,  MD  20722 \n\nAbstract \n\nRecent  physiological  research  has  shown  that  synchronization  of \noscillatory  responses  in  striate  cortex  may  code  for  relationships \nbetween  visual  features  of objects.  A  VLSI  circuit  has  been  de(cid:173)\nsigned  to  provide  rapid  phase-locking  synchronization of multiple \noscillators to allow for further exploration of this neural mechanism. \nBy  exploiting the  intrinsic  random transistor  mismatch of devices \noperated  in  subthreshold,  large  groups  of phase-locked  oscillators \ncan  be  readily  partitioned  into  smaller  phase-locked  groups.  A \nmUltiple target  tracker for  binary images is described  utilizing this \nphase-locking  architecture.  A  VLSI  chip  has  been  fabricated  and \ntested  to  verify  the  architecture.  The  chip  employs  Pulse  Ampli(cid:173)\ntude  Modulation  (PAM)  to encode  the output at  the  periphery  of \nthe system. \n\n1 \n\nIntroduction \n\nIn striate  cortex,  visual  information coming from  the  retina  (via the  lateral  genic(cid:173)\nulate nuclei)  is  processed  to extract  retinotopic maps of visual features.  Some cells \nin  cortex are  receptive  to  lines  of particular orientation,  length,  and/or  movement \ndirection  (Hubel,  1988).  A  fundamental  problem  of  visual  processing  is  how  to \n\n866 \n\n\fVLSI Phase Locking Architectures for Feature Linking in Multiple Target Tracking Systems \n\n867 \n\nassociate  certain  groups  of features  together  to  form  coherent  representations  of \nobjects.  Since  there  is  an  almost infinite  number of possible feature  combinations, \nit seems  unlikely  that  there  are  dedicated  \"grandmother\"  cells  which  code for  ev(cid:173)\nery  possible  feature  combination.  There  probably  exists  a  type  of adaptive  and \ntransitory method to  \"bind\"  these  features  together.  The  Binding  Problem (Crick, \n1990)  is  the problem of making neural elements which  are receptive  to these  visual \nfeatures  temporarily  become  active  as  a  group  that  codes  for  a  particular  object, \nyet  maintaining the  group's  specificity  towards  that  object,  even  when  there  are \nseveral  different  interleaved objects in the visual field. \n\nTemporal  correlation  of  neural  response  is  one  solution  to  the  binding  problem \n(von  der  Malsburg,  1986).  Response  from  neurons  (or  neural  oscillating  circuits) \nwhich are receptive to a particular visual feature are required to have high temporal \ncorrelation  with  responses  to  other  visual  features  that  correspond  to  the  same \nobject.  This would require  that there is stimulus-driven oscillation in visual cortex, \nand that there is  also a degree of oscillation synchronization between neural circuits \nreceptive  to the same object.  Both of these  requirements have  been found in visual \ncortex  (Gray,  1987;  Gray,  1989).  Furthermore,  there  have  been  several  computer \nsimulations of the  synchronization  phenomena and  related  visual  processing  tasks \n(Baldi,  1990;  Eckhorn,  1990). \n\nThis  paper  describes  a  phase-locking  architecture  for  a  circuit  which  performs  a \nmultiple-target tracking problem.  It will accomplish this task by establishing a zero \nvalued phase difference  between oscillators that are receptive to those features to be \n\"bound\"  together to form an object.  Each object will then be recognized  as a group \nof synchronous  oscillators,  and  oscillators  that  correspond  to  different  objects  will \nbe  identified  due  to their lack of synchronization.  We  assume these  oscillators have \nlow  duty-cycle  pulsed  outputs,  and  the  oscillators  which  correspond  to  the  same \nobject  will  all  pulse  high  at the same time.  Target location  will  be  communicated \nto  the  periphery  by  Pulse Amplitude Modulation (PAM). \n\n2  The Neural  Oscillator \n\nThe oscillator for  the target tracker must have two qualities.  It needs  to be capable \nof producing  a  fairly  smooth  phase  representation  so  that  it  is  easy  to  compare \nthe  difference  between  oscillator phases to allow for  robust phase-locking.  It is  also \nuseful  to have a pulsed output present so that one group of oscillators can be easily \ndiscerned  from  another  group of oscillators when  their  outputs  are  examined over \ntime.  The self-resetting neuron circuit (Mead,  1989) provides both of these outputs \n(Figure  1).  Current  lin  provided  by  FET  Ql  charges  capacitor  Cl  until  positive \nfeedback  though the non-inverting CMOS amplifier and capacitor C2 brings  V p ha.ge \nall  the  way  to  Vdd.  This causes  the  output voltage  to go  high,  which  turns  on  Q2 \nthus  draining  charge  from  Cl  by  I reret  through  Q3  and  lowering  V pha.ge.  When \nthe  Vpha\"e  is  brought  low  enough,  positive  feedback  brings  both  Vpha\"e  and  the \noutput  voltage  down  to  Vu.  This  turns  transistor  Q2  off,  and  the  cycle  repeats. \nThe duration of output pulses is  inversely  proportional to  Irelet  -\nlin,  and the time \nbetween  output  pulses  is  inversely  proportional  to  lin.  Figure  2  is  a  plot  of the \npulse output voltage  and  Vphale  vs.  time. \n\n\f868 \n\nAndreou and Edwards \n\nVphase f - - -..... \n\n---~ Pulse \nOutput \n\nFigure  1:  Self-Resetting  Neural  Oscillator \n\n5 \n\n,..... \n\n\\ \n\\ \nI \n\n, \n\n\\ \n\\ \n\nOscillator Output \n\n,..... \n\n\\ \nI \n\\ \nI \n\\ \n\\ \n\n,..... \n\nI \n\\ \n\\ \nI \n\\ \n\\ \n\n,..... \n\n\\ \n\\ \n\\ \n\\ \n\\ \n\\ \n\nI \n\nI \nI \nI \nI \nI \nI \n\n/ \n\no \n\nI \nI \nI \nI \nI \nI \nI \n\n, \nv \n\nJ \n\nI \nI \nI \nI \nI \nI \nI \nI \nI \n\nI \n\nI \nI \nI \nI \nI \nI \nI \nI \nJ \nv \n\nI \nI \nI \nI \nI \nI \nI \n\nI \n\n-1+---~--~---r--~--~----~--+---~---r--~ \n9 \n\no \n\n-1 \n\n1 \n\n5 \n\n2 \n\n4 \n\n3 \n(lO-6 sec) \n\n6 \n\n7 \n\n8 \n\nFigure  2:  Plot  of Pulse  Output  (line)  and  Phase  Voltage  (dashed)  vs.  Time for \nNeural  Oscillator \n\n\fVLSI Phase Locking Architectures for Feature Linking in Multiple Target Tracking Systems \n\n869 \n\n3  Phase Locking \n\nTo achieve stable and reliable performance, the  Comparator Model (Kammen, 1990) \nof phase-locking was used.  Oscillator phase is  adjusted  according  to \n\naO(x,t) \n\nat  =w(x)+!  ;f;;t0(\"t)-O(x,t) \n\n(1~ . \n\n) \n\n. \n\nWhere  O( x, t)  is  the  phase  of oscillator  x  at  time  t,  w( x)  is  the  intrinsic  phase \nadvance  of oscillator  x,  n  is  the  total  number  of oscillators,  and  !  is  a  sigmoid \nsq uashing-function. \n\nEach object in the visual field requires one averaging circuit to achieve phase-locking \nof its receptive oscillators.  But  at any  time we  do not know  the number of objects \nwhich  will  be  in  the  visual field.  Therefore,  instead  of having a  pool of monolithic \naveraging  circuits,  it  is  preferable  to distribute  the  averaging function  over  all  the \noscillator  cells  in  a  way  which  allows  partitioning of the  visual  field  into  multiple \nphase-locked groups of oscillators.  The follower-aggregator circuit (Mead,  1989) can \nbe used  to develop  the average phase information using current-mode computation. \nIt consists  of transconductance  amplifiers  connected  as  voltage-followers  with  all \noutputs tied  together  to form the  average of all  input  voltages. \n\nThe phase  averaging circuitry  can  be  distributed  among the  oscillators  by  placing \none  transconductance  amplifier in each  oscillator  cell,  and  linking those  oscillators \nto  be  phase-locked  by  a  common  line.  The  visual  field  can  be  partitioned  into \nmultiple phase-locked  groups  with separate  average  phases  by  using  FETs  to  gate \nwhether  or not  the  averaging  information can pass through  an oscillator cell  to its \nneighbors. \n\nTo lock  an oscillator in phase with the rest  of the oscillators which  are  attached  to \nthe averaging line, extra current is provided to the oscillator by  a  transconductance \namplifier  to  slightly  speed  up  or  slow  down  the  oscillator  to  match  its  phase  to \nthe  average  phase  of the oscillators  in  the  group.  Figure  3 shows  t.he  circuit  for  a \ncomplete phase-locking oscillator cell. \n\nComputer simulations of this phase-locking system were carried out  using the Ana(cid:173)\nlog  circuit  simulator.  Figure  4  shows  the  result  of a  simulation of two  oscillators. \nVgate  is  the voltage controlling the  NFET of the  transmission gate which  links  the \nphase  averaging  lines  of the  two  oscillators  together  (the  PFETs  are  controlled \ncomplementary).  As  soon as the Vgate  is  brought high, the oscillat.ors rapidly phase \nlock. \n\n4  Target  Location \n\nWe will  assume that the input to a  visual tracking chip is  a  binary image projected \nonto the die.  Phototransistors detect  the brightness of each pixel,  and if it is  above \na  threshold  level,  the pixel  control  circuitry  will  turn  the  pixel's oscillator  on.  If a \npixel oscillator is turned on, gating circuitry will allow the propagation of the phase \naveraging line through the pixel's oscillator cell to its nearest-neighbors.  Illuminated \n\n\f870 \n\nAndreou and Edwards \n\nTo top neighbor \n\nv \u2022\u2022 ~~ \n\nTo left  -_4  \nneighbor  T. \n\n. - - - - - - - - - To right \n\nneighbor \n\nVgateP~  ,,-+--~< VgateN \n\nVf>-1 \n\nTo bottom neighbor \n\nPulse \nOutput \n\nFigure 3:  Phase-Locking Oscillator Cell \n\n\fVLSI Phase Locking Architectures for Feature Linking in Multiple Target Tracking Systems \n\n871 \n\nSp1ke2~-...J \n\nI--------i \n\n-5 \n\n10  sec \n\nFigure 4:  Phase-Locking Simulation \n\nnearest-neighbor connected pixels will thus have their oscillators turned on and will \nbecome phase-locked. \nThe follower-aggregator circuit can be modified to determine linear position (Maher, \n1989) by  using voltage taps off of a  resistive  line as  inputs to the  transconductance \namplifiers,  and  biasing  the  amplifiers  by  currents  that  correspond  to  the  pulsing \noutputs of the oscillators (see  Figure 5). \n\nDuring the  time that  a group  of oscillators are  spiking,  the  output of the tracking \ncircuitry will yield a  location corresponding to the average position of the distribu(cid:173)\ntion of those  oscillators.  There  can  be  many  different  nearest-neighbor  connected \nobjects projected onto the die,  and the position of the  center of each object is com(cid:173)\nmunicated  to  the  periphery  via  PAM.  Thus,  we  can  use  multiplexing  in  time  to \nsimplify connectivity of communication with the  periphery  of the  chip. \n\n5  Test  Chip \n\nA  chip  to  test  the  Comparator  Model  phase-locking  method  and  multiple-target \ntracking system was fabricated by the MOSIS service in 2.0 J1.m  feature size CMOS. \nTo  keep  this  test  chip  simple,  the  oscillators  were  arranged  in  a  one-dimensional \nchain,  and  voltage  inputs  to  the  chip  were  used  to  control  whether  or  not  a  pixel \nwas considered  \"illuminated.\"  A polysilicon resistive line was used  to provide linear \nposition  information  to  the  tracking  system.  All  transistors  used  were  minimum \nsize  (6  J1.m  wide  and 4 J1.m  long). \n\nThe test chip was able to rapidly and robustly phase-lock groups of nearest-neighbor \n\n\f872 \n\nAndreou and Edwards \n\nPostional Voltage Line \n\nVpulse(n-l) \n\nVpulse(n) \n\nVpulse(n+l) \n\nAverage Position Line \n\nFigure  5:  Circuit to determine object location \n\nconnected oscillators.  This phase-locking could occur with oscillator frequencies  set \nfrom  10  Hz  to 4  KHz.  A  phase-locked  group  of oscillators  would  almost  instantly \nsplit into two separate phase-locked groups with little temporal correlation between \nthem when a connected chain of on oscillators was severed by turning off an oscillator \nin  the  middle  of the  original  group .  Mismatch  in  the  transconductances  of  the \noscillator transistors  provided easy  desynchronization. \n\nPosition tracking  was  measured  by  examining  the  resistive-line  aggregator  output \nduring  the  time  a  certain  phase-locked  group  of oscillators  was  pulsing .  When \nmultiple  phase-locked  groups  of oscillators  were  active,  it  was  still  quite  easy  to \nmake out  the positional  PAM  voltage associated  with each  group  by  triggering  an \noscilloscope off of the pulsing output of an oscillator in that group.  While there are \noccasional  instances  of two  or  more  groups  pulsing  at  the  same  time,  if the  duty \ncycle  of the spiking oscillator is  kept  relatively small, there  is  little interference  on \naverage. \n\n6  Discussion \n\nIt is  becoming obvious  that  oscillation  and  synchronization  phenomena in  cortex \nmay play an important role in neural information processing.  In addition to striate \ncortex,  the olfactory bulb also  has oscillatory neural  circuits  which  may be  impor(cid:173)\ntant in neural information processing  (Freeman,  1988) .  It has been suggested  that \ntemporal correlation may be used  for  pattern segmentation in associative memories \n(Wang, 1990), and correlations between multiple oscillators may be used for  storing \ntime intervals (Miall,  1989). \n\nWe  have described  a circuit which  performs Comparator Model phase-locking.  The \ndistributed and partitionable qualities of this circuit make it attractive as a possible \nphysiological model.  The PAM representation of object position shows one way that \nconnectivity requirements can be minimized for  communication in  a  neuromorphic \n\n\fVLSI Phase Locking Architectures for Feature Linking in Multiple Target Tracking Systems \n\n873 \n\nsystem.  The  chip  has  been  fabricated  using  subthreshold  CMOS  technology,  and \nthus uses  little power. \n\nAcknowledgements \n\nThe  authors  are  pleased  to  acknowledge  helpful  discussion  with  C.  Koch  and  J. \nLazzaro.  Chip fabrication was provided  by  the MOSIS  service. \n\nReferences \n\n(1990)  Towards  a  neurobiological  theory  of consciousness. \n\nP.  Baldi & R.  Meir.  (1990)  Computing with  arrays of coupled oscillators:  an appli(cid:173)\ncation to preattentive texture  discrimination.  Neural  Computation  2,  458-47l. \nF.  Crick  &  C.  Koch. \nSeminars  in  the  Neurosciences 2, 263-275. \nR.  Eckhorn,  H.  J.  Reitboek,  M.  Arndt  &  P.  Dicke. \n(1990)  Feature  linking  via \nsynchronization among distributed assemblies:  simulations of results from cat visual \ncortex.  Neural  Computation  2,  293-307. \nW. J.  Freeman, Y. Yao,  & B. Burke.  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