{"title": "Implementing Intelligence on Silicon Using Neuron-Like Functional MOS Transistors", "book": "Advances in Neural Information Processing Systems", "page_first": 919, "page_last": 926, "abstract": null, "full_text": "Implementing Intelligence  on Silicon \n\nUsing  Neuron-Like Functional  MOS  Transistors \n\nTadashi  Shibatat  Koji  Kotani t  Takeo  Yamashitat  Hiroshi  Ishii \n\nHideo  Kosaka t  and Tadahiro  Ohmi \nDepartment  of Electronic  Engineering \n\nAza-Aoba,  Aramaki,  Aobaku,  Sendai  980  lAP AN \n\nTohoku  University \n\nAbstract \n\nWe  will  present  the  implementation  of  intelligent  electronic  circuits \nrealized  for  the  first  time  using  a new  functional  device  called  Neuron \nMOS  Transistor  (neuMOS  or vMOS  in  short)  simulating  the  behavior \nof biological  neurons  at  a  single  transistor  level.  Search  for  the  most \nresembling  data \nin  the  memory  cell  array,  for  instance,  can  be \nautomatically \nsoftware \nmanipulation.  Soft Hardware,  which  we named,  can  arbitrarily  change \nits  logic  function  in  real  time  by  external  control  signals  without  any \nhardware  modification.  Implementation  of a  neural  network  equipped \nwith  an on-chip  self-learning  capability  is also  described.  Through  the \nstudies  of  vMOS  intelligent  circuit  implementation,  we  noticed  an \ninteresting  similarity  in  the  architectures  of vMOS  logic  circuitry  and \nbiological  systems. \n\ncarried  out  on  hardware  without  any \n\n1  INTRODUCTION \nThe  motivation  of  this  work  has  stemmed  from  the  invention  of  a  new  functional \ntransistor  which  simulates  the  behavior  of biological  neurons  (Shibata  and  Ohmi,  1991; \n1992a).  The  transistor  can  perfOlID  weighted  summation  of multiple  input  signals  and \nsquashing  on  the  sum all  at  a single  transistor  level.  Due  to  its functional  similarity,  the \ntransistor  was  named  Neuron  MOSFET  (abbreviated  as  neuMOS  or vMOS).  What  is  of \nsignificance  with this  new  device  is that a number  of new  architecture  electronic  circuits \ncan  be build using vMOS' which  are different  from conventional  ones both  in  operational \nprinciples  and  functional  capabilities.  They  are  charactetized  by  a  high  degree  of \nparallelism  in hardware  computation,  a large  flexibility  in  hardware  configuration  and  a \ndramatic  reduction  in  the  circuit  complexity  as  compared  to  conventional  integrated \n\n919 \n\n\f920 \n\nShibata, Kotani, Yamashita, Ishii, Kosaka, and Ohmi \n\ncircuits.  During the course of studies in exploring vMOS circuit applications  an interesting \nsimilarity  has  been  noticed  between  the  basic  vMOS  logic  circuit  architecture  and  the \ncommon  structure  found  in  biological  neuronal  systems,  i.  e.,  the  competitive  processes \nof excitatory  and inhibitory  connections.  The purpose of this article  is to demonstrate  how \npowerful  the  neuron-like  functionality \nin  an  elemental  device  is  in  implementing \nintelligent  functions  in  silicon  integrated  circuits. \n\n2  NEURON MOSFET AND SOFT-HARDWARE LOGIC CIRCUITS \nThe  symbolic  representation  of a vMOS  is  given  in  Fig.  1.  A vMOS  is  a regular  MOS \ntransistor  except  that  its  gate  electrode  is  made  electrically  floating  and  multiple  input \nterminals  are  capacitively  coupled  to  the  floating  gate.  The  potential  of the  floating  gate \n~ is  determined  as  a  linear  weighted  sum  of  multiple  input  voltages  where  each \nweighting  factor  is  given  by  the  magnitude  of a  coupling  capacitance.  When  <l>F'  the \nweighted  sum,  exceeds  the  threshold  voltage  of the  transistor,  it  turns  on.  Thus  the \nfunction  of a neuron  model  (McCulloch  and  Pitts,  1943) has  been  directly  implemented \nin  a  simple  transistor  structure.  vMOS  transistors  were  fabricated  using  the  double(cid:173)\npolysilicon  gate  technology  and  a  CMOS  process  was  employed  for  vMOS  integrated \ncircuits  fabrication.  It  should  be  noted  here  that  no  floating-gate  charging  effect  was \nemployed  in  the  operation  of vMOS  logic  circuits. \n\nV,  v2 \nvn \n1.1.---------J. \n\n4>F  \" \n_...-J,I \n\n'\" ~ FLOATING  GATE \n\nc v. +C V.  +\u00b7\u00b7\u00b7\u00b7\u00b7+C  V \n\nCl>F-\n\n1  1 \n\n2  2 \nCror \n\nn  n \n\n)  V  ~ \n\nSOURCE \n\nDRAIN \n\nTransistor  \"Turns ON\" \n\nFigure  1:  Schematic  of a neuron  MOS  transistor. \n\nSince  the  weighting  factors  in  a vMOS  are  detennilled  by  the  overlapping  areas  of the \nfirst  poly (floating  gate)  and  second  poly (input  gate) patterns,  they  are not alterable.  For \nthis  reason,  in  vMOS  applications  to  self-learning  neural  network  synthesis,  a  synapse \ncell  circuit  was  provided  to  each  input  temlinal  of a  vMOS  to  represent  an  alterable \nthe  plasticity  of  a  synaptic  weight  was  created  by \nconnection  strength.  Here \ncharging/discharging  of the floating-gate  in  a vMOS  synapse  circuitry  as described  in  4. \nTheI-Vcharacteristics  ofa two-input-gate vMOS having identical  coupling capacitances \nare  shown  in Fig.  2, where  one of the  input  gates  is  used  as  a gate  terminal  and  the  other \nas  a  threshold-control  terminal.  The  apparent  threshold  voltage  as  seen  from  the  gate \nterminal  is  changed  from  a  depletion-mode  to  an  enhancement-mode  threshold  by  the \nvoltage  given  to  the  control  terminal.  This  variable  threshold  nature  of a  vMOS,  we \nbelieve,  is  most  essential  in  creating  flexibility  in  electronic  hardware  systems. \nFigure  3(a)  shows  a two-input-variable  Soft  Hardu:are  Logic  (SHL)  circuit  which  can \nrepresent  all  possible  sh.1een  Boolean  functions  for  two  binary  inputs  Xl  and  X2  by \nadjusting  the  control  signals  VA'  VB  and  Ve.  The  inputs,  Xl  and  X2,  are  directly  coupled \nto  the  floating  gate  of a  complementary  vMOS  inverter  in  the  output  stage  with  a  1:2 \ncoupling ratio.  The vMOS inve11er,  which we call  the main  inve11er,  deternlines  the logic. \n\n\fImplementing Intelligence on Silicon Using Neuron-Like Functional MOS Transistors \n\n921 \n\nFigure  2:  Measured  char(cid:173)\nacteristics  of  a  variable \nthreshold  transistor.  Vol(cid:173)\ntage  at the threshold-con(cid:173)\ntrol  tenninal  was  varied \nfrom  +5V  to  -5V  (from \nleft  to  right). \n\n5 0 \n\n-2.5 \nGATE  VOLTAGE  (V) \n\n2.5 \n\n0.0 \n\nx , o---.,----t \nX2 o--~----t \n\n(a) \n\n(b) \n\nOms \n\n2ms/div \n\n20ms \n\nTwo-input-variable \n\nFigure  3: \nlogic  circuit(a)  and  measured \ncharacteristics(b).  The  slow  operation  is due to  the loading  effect.  (The test  circuit  has no \noutput  buffers.) \n\nsoft  hardware \n\nThe  inputs  are  also  coupled  to  the  main  inve11er  via  three  inter-stage  vMOS  inverters \n(pre-inverters).  When  the  analog  variable  represented  by  the  binary  inputs  Xl  and  X2 \nincreases~  the  inputs  tend  to  turn  on  the  main  inverter  via  direct  connection~  while  the \nindirect  connection  via  pre-inverters  tend  to  turn  off the  main  invelter  because  pre(cid:173)\ninverter outputs change  from  V DO to 0 when they  turn on. This competitive  process creates \nlogics.  The  turn-on  thresholds  of pre-inverters  are  made  alterable  by  control  signals \nutilizing  the variable  threshold  characteristics  of vMOS'.  Thus the  real-time  alteration  of \nlogic functions  has been achieved  and are demonstrated  by experiments  in Fig. 3(b). With \nthe basic circuit architecture  of the two-staged vMOS inverter configuration  shown in Fig. \n3(a)~ any Boolean function  can be generated.  We found the inverting  connections  via pre(cid:173)\ninverters  are  most  essential  in  logic  synthesis.  The  structure  indicates  an  interesting \nsimilarity  to  neuronal  functional  modules  in  which  intramodular  inhibitory  connections \nplay  essential  roles. \nFixed  function  logics  can  be  generated  much  more  simply  using  the  basic  two-staged \nstructure~ resulting  in a dramatic  reduction  in transistor  counts and  interconnections.  It has \nbeen  demonstrated  that  a full  adder~ 3-b and  4-b NO conve11ers  can be constructed  only \nwith  8~ 16 and  28  transistors~ respectively,  which  should  be  compared  to  30~ 174 and  398 \ntransistors  by  conventional  CMOS  design,  respectively.  The  details  on  vMOS  circuit \ndesign  are  desClibed  in  Refs.  (Shibata  and  Ohmi,  1993a;  1993b)  and  experimental \nverification  in  Ref.  (Kotani  et  al.~  1992). \n\n\f922 \n\nShibata, Kotani, Yamashita, Ishii, Kosaka, and Ohmi \n\nVoo \n\np \n\np \n\nX \ny \n\n( \n\nAnalog \nInverter  ~ ~ \n\n60 \\:c N  r N \n\nINPUT \n\n'\" \n~ \n:::. \n'\" \n1 \n\nVOUT \n\nOUTPUT \n\n:::. \n\n'\" ~1 \n'\" \n\n'\" \n-01 \n~ \n\nIt) \n\n+-+  2msec/dlv \n\n+--+  Smsec/dlv \n\n(a) \n\n(b) \n\n(c) \n\nFigure  4:  Real-time  rule-variable  data  matching  circuit  (a)  and  measured  wave  forms \n(b  &  c).  In  (c),  l)  is  changed  as  0.5,  1,  1.5, and  2  [V]  from  top  to  bottom. \n\nA  unique  vMOS  circuit  based  on  the  basic  structure  of Fig.  3(a)  is  the  real-time  rule(cid:173)\nvariable  data matching  circuitry  shown in Fig. 4(a). The circuit output becomes  high when \nI X - y I < l).  X is  the  input  data,  Y the  template  data  and  l) the  window  width  for  data \nmatching  where  X, Y and  l) are all  time  variables.  Measured  data  are  shown  in  Figs.  4(b) \nand  4(c),  where  it  is  seen  the  triple  peaks  are  merged  into  a single  peak  as  l)  increases \n(Shibata  et  al.,  1993c).  The  circuit  is  composed  of only  10  vMOS'  and  can  be  easily \nintegrated  with  each  pixel  on  a  image  sensor  chip.  If vMOS  circuitry  is  combined  with \na  bipolar  image  sensor  cell  having  an  amplification  function  (fanaka  et  al.,  1989),  for \ninstance, in situ  image  processing  such as edge detection  and variable-template  matching \nwould  become  possible,  leading  to  an  intelligent  image  sensor  chip. \n\n3  BINARY-MULTIVALUED-ANALOG  MERGED  HARDWARE \nCOMPUTATION \nA  winner-take-all  circuit  (WTA)  implemented  by  vMOS  circuitry  is  given  in  Fig.  5. \nEach  cell  is  composed  of  a  vMOS  variable  threshold  inverter  in  which  the  apparent \nthreshold  is modified  by an analog  input  signals VA - V c' When  the  common  input  signal \nVR is ramped  up, the  lowest threshold  cell  (a cell  receiving  the largest  analog  input)  turns \non  firstly,  at  which  instance  a  feedback  loop  is  formed  in  each  cell  and  the  state  of the \ncell  is self-latched.  As a result,  only the winner  cell yields  an  output of 1. The circuit  has \nbeen applied  to building an associative  memory  as demonstrated  in Fig. 6. The binary data \nstored  in  a SRAM cell  array  are  all  simultaneously  matched  to the  sample  data  by  taking \nXNOR, and  the number  of matched  bits are  transfeITed  to  the floating  gate  of each  WfA \ncell by capacitance  coupling. The WI' A action finds  the location  of data having the largest \nnumber  of matched  bits.  This  principle  has  been  also  applied  to  an  sorting  circuitry \n(Yamashita  et aI.,  1993). In these  circuits  all  computations  are conducted  by an algOlithm \ndirectly  imbedded  in the hardware.  Such an analog-digital  merged hardware  computation \nalgorithm  is  a  key  to  implement  intelligent  data  processing  architecture  on  silicon.  A \nmultivalued  DRAM cell  equipped  with the association  function  and a multivalued  SRAM \ncell  having  self-quantizing  and  self-classification  functions  have  been  also  developed \nbased  on  the  binary-multivalued-analog  merged  hardware  algorithm  (Rita  et  aI.,  1994). \n\n\fImplementing Intelligence on Silicon Using Neuron-Like Functional MOS Transistors \n\n923 \n\nINITIAL \n\nWINNER LATCH \n\nV~o  ~1 \n\nV'~  VR  V~o VR  ~o CONTROL \nV~o  ~o  SIGNAL \n\nTIME \n\nFigure  5:  Operational  principle  of vMOS  Winner-Take-All  circuit. \n\n- 0 \n- 1 \n\n0  ~ \n~ \ng] \n.... \n0  a \nc:  -\n=ti c: \n0 \n.... \n...., \n0 \n-\n\n+  t  t  !  t \no \n1 \nSAMPLE DATA \n\nfr \n\nWINNER- TAKE-ALL \n\nNETWORK \n\n(a) \n\n(b) \n\nFigure  6:  vMOS  associative  memory:  (a) circuit  diagram;  (b) photomicrograph  of a test \nchip. \n\nis  due  to \n\nthe  plasticity  of  synaptic  connections.  Therefore \n\n4  HARDWARE SELF-LEARNING NEURAL NETWORKS \nSince  vMOS  itself  has  the  basic  function  of  a  neuron,  a  neuron  cell  is  very  easily \nimplemented  by  a  complementary  vMOS  inve11er.  The  learning  capability  of a  neural \nnetwork \nits  circuit \nimplementation  is  a key  issue.  A stand-by  power  dissipation  free  synapse  circuit  which \nhas  been  developed  using  vMOS  circuitry  is  shown  in  Fig.  7(a).  The  circuit  is  a \ndifferential  pair  of N-channel  and  P-channel  vMOS  source  followers  sharing  the  same \nfloating  gate,  which  are  both  merged  into  CMOS  inverters  to  cut  off dc  cunent  paths. \nWhen the  pre-synaptic  neuron  fires,  both source followers  are activated.  Then  the  analog \nweight  value  stored  as  charges  in  the  common  floating  gate  is read  out and  transferred  to \nthe  floating gate (dendrite)  of the post-synaptic  neuron  by capacitance  coupling  as shown \nin  Figs.  7 (b)  and  (c).  The outputs  of N-vMOS  (V+)  and  P-vMOS  (V-) source followers \nare  averaged  at  the  dendrite  level,  yielding  an  effective  synapse  output  equal  to  (V+  + \nV-)/2.  The  synapse  can  represent  both  positive  (excitatory)  and  negative  (inhibitory) \nweights  depending  on  whether  the  effective  output  is  larger  or  smaller  than  Vnrj2, \nrespectively.  The  operation  of the  synapse  cell  is  demonstrated  in  Fig.  8(a). \n\n\f924 \n\nShibata, Kotani, Yamashita, Ishii, Kosaka, and Ohmi \n\nP-UMOS \n\n\u2022 I \n\ntunneling \nelectrode \n\nV-\n\nV-\n\nT \n\n7 \n\nFLOATING GATE (DENDRITE) OF NEURON \n\n(a) \n\nPrevious Neuron at Rest \n\nPrevious Neuron Fired \n\nv\"\" \n\nv .. \n\nv-\n\nVoo \nV  = -\n2 \n\n.\" \n\n(b) \n\n(c) \n\nFigure  7:  Synapse  cell  circuit  implemented  by  vMOS  circuitry. \n\nVI \n\n......... \n\nv-\n\nV+ \n\nVDD \n\n0 \n\nVoe \nYlm. \n2 \n0 \n\nVeo \n\nVoe \n2 \n0 \n\nPrevious-Layer Neuron \n\nFired \n\nEXCITATORY \n\nV+  +  V-\n\n2 \n\nINHIBITORY \n\nv-\n\n0 \n\nV+ \n\nV\" +  V-\n\n2 \n\nCONVENTIONAL CELL \n\n3~----------------~ \n2 \n1 \n>,0 \n\"';-1 \n:> -2 \n-3 \n-4 \n\nNEW CELL \n\n4 \n3 \n\n~2 \nx  1 \n:>  0 \n-1 \n-2 \no \n\n_3L-~L-~--~---L--~ \n25 \nNumber of Programming Pulses \n\n20 \n\n5 \n\n10 \n\n15 \n\nf t= \n\n-~ \n\n400nsec \n\n(a) \n\n(b) \n(a)  Measured  synapse  cell  output  characteristics; \n\nFigure  8: \n(b)  weight  updating \ncharacteristics  as  represented  by  N-vMOS  threshold  with  (our  new  cell:bottom)  or \nwithout  (conventional  EEPROM  cell:  top)  feed  back. \n\nThe weight updating  is conducted  by giving high  programming  pulses to both V x and V y \ntenninals.  (Their  coupling  capacitances  are  made  much  larger  than  others).  Then  the \ncommon floating  gate is pulled up to the programming  voltage~ allowing  electrons  to flow \ninto  the  floating  gate  via  Fowler-Nordheim  tunneling.  When  either  Vx  or  Vy  is  low, \ntunneling  injection  does  not  occur because  the  tunneling  current  is  very  sensitive  to  the \nelectric  field  intensity,  being exponentially  dependent  upon the  tunnel  oxide field  (Hieda \n\n\fImplementing Intelligence on  Silicon Using Neuron-Like Functional MOS Transistors \n\n925 \n\n(HEP)  learning  algorithm~  which \n\net  al.~  1985).  The  data  updating  occurs  only  at  the  crossing  point  of Vx  and  Vy  lines~ \nallowing  Hebb-rule-like  learning  directly  implemented  on  the  hardware  (Shibata  and \nOhmi~  1992b).  Hardware-Backpropagation \nis  a \nsimplified  version  of the  original  BP ~  has  been  also  developed  in  order  to  facilitate  its \nhardware  implementation  (Ishii  et  al.~  1992) and  has  been  applied  to  build  self-learning \nvMOS  neural  networks  (Ishii  et  al.~  1993). \nOne  of  the  drawbacks  of  programming  by  tunneling  is  the  non-linearity  in  the  data \nupdating  characteristics  under  constant  pulses  as  shown  in Fig.  8(b) (top). This difficulty \nhas been  beautifully  resolved  in our cell.  With Vs high~ the  output of the N-vMOS source \nfollower  is fed  back to the tunneling  electrode  and  the floating-gate  potential  is set to the \ntunneling  electrode.  In this manner~ the voltage  across the tunneling oxide is always preset \nto  a  constant  voltage  (equal  to  the  N-vMOS  threshold)  before  a  programming  pulse  is \napplied~ thus  allowing  constant  charge  to  be  injected  or extracted  at  each  pulse  (Kosaka \net al~ 1993) as demonstrated  in Fig. 8(b) (bottom).  A test self-learning  circuit  that leamed \nXOR  is  shown  in  Fig.  9. \n\nINPUT1 \n\nINPUT2 \n\n\"XOR\" \n\nI \n\nI \nJI-; ---\"~ \n; \n\n! \n\nINPUT1 \\l \n\n[ \nINPUT2 ! \n\n400nsecldiv \n\nFigure  9:  Test  circuit  of vMOS  neural  network  and  its  response  when  XOR  is  learnt. \n\n5  SUMMARY \nDevelopment  of intelligent  electronic  circuit  systems using a new functional  device  called \nNeuron  MOS  Transistor  has  been  described.  vMOS circuitry  is  charactedzed  by  its  high \nparallelism  in computation  scheme  and the large flexibility  in altering  hardware  functions \nand also by its great simplicity  in the circuit  organization.  The ideas of Soft Hardware  and \nthe  vMOS  associative  memory  were  not  directly  inspired  from  biological  systems. \nHowever~ an interesting  similarity  is found  in their basic structures.  It is also demonstrated \nthat  the  vMOS  circuitry  is  very  powerful  in  building  neural  networks  in  which  learning \nalgorithms  are imbedded  in the hardware.  We conclude  that the neuron-like  functionality \nat  an  elementary  device  level  is  essentially  imp0l1ant  in  implementing  sophisticated \ninformation  processing  algorithms  directly  in  the  hardware. \n\n\f926 \n\nShibata, Kotani, Yamashita, Ishii, Kosaka, and Ohmi \n\nACKNOWLEDGMENT \nThis  work  was  paltially  supported  by  the  Grant-in-Aid  for  Scientific  Research \n(04402029)  and  Grant-in-Aid  for  Developmental  Scientitlc  Research  (05505003)  from \nthe  Ministry  of Education,  Science  and  Culture,  Japan.  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Dig.,  1993,  pp.  626-626. \n\n\f", "award": [], "sourceid": 725, "authors": [{"given_name": "Tadashi", "family_name": "Shibata", "institution": null}, {"given_name": "Koji", "family_name": "Kotani", "institution": null}, {"given_name": "Takeo", "family_name": "Yamashita", "institution": null}, {"given_name": "Hiroshi", "family_name": "Ishii", "institution": null}, {"given_name": "Hideo", "family_name": "Kosaka", "institution": null}, {"given_name": "Tadahiro", "family_name": "Ohmi", "institution": null}]}