A Reconfigurable Analog VLSI Neural Network Chip

Part of Advances in Neural Information Processing Systems 2 (NIPS 1989)

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Srinagesh Satyanarayana, Yannis Tsividis, Hans Graf


1024 distributed-neuron synapses have been integrated in an active area of 6.1mm x 3.3mm using a 0.9p.m, double-metal, single-poly, n-well CMOS technology. The distributed-neuron synapses are ar(cid:173) ranged in blocks of 16, which we call '4 x 4 tiles'. Switch matrices are interleaved between each of these tiles to provide programma(cid:173) bility of interconnections. With a small area overhead (15 %), the 1024 units of the network can be rearranged in various configura(cid:173) tions. Some of the possible configurations are, a 12-32-12 network, a 16-12-12-16 network, two 12-32 networks etc. (the numbers sep(cid:173) arated by dashes indicate the number of units per layer, including the input layer). Weights are stored in analog form on MaS ca(cid:173) pacitors. The synaptic weights are usable to a resolution of 1 % of their full scale value. The limitation arises due to charge injection from the access switch and charge leakage. Other parameters like gain and shape of nonlinearity are also programmable.