{"title": "A Summating, Exponentially-Decaying CMOS Synapse for Spiking Neural Systems", "book": "Advances in Neural Information Processing Systems", "page_first": 1003, "page_last": 1010, "abstract": "", "full_text": "A Summating, Exponentially-Decaying CMOS\n\nSynapse for Spiking Neural Systems\n\nRock Z. Shi1,2 and Timothy Horiuchi1,2,3\n\n1Electrical and Computer Engineering Department\n\n2Institute for Systems Research\n\n3Neuroscience and Cognitive Science Program\n\nUniversity of Maryland, College Park, MD 20742\n\nrshi@glue.umd.edu,timmer@isr.umd.edu\n\nAbstract\n\nSynapses are a critical element of biologically-realistic, spike-based neu-\nral computation, serving the role of communication, computation, and\nmodi\ufb01cation. Many different circuit implementations of synapse func-\ntion exist with different computational goals in mind. In this paper we\ndescribe a new CMOS synapse design that separately controls quiescent\nleak current, synaptic gain, and time-constant of decay. This circuit im-\nplements part of a commonly-used kinetic model of synaptic conduc-\ntance. We show a theoretical analysis and experimental data for proto-\ntypes fabricated in a commercially-available 1.5\u00b5m CMOS process.\n\n1\n\nIntroduction\n\nSynapses are a critical element in spike-based neural computation. There are perhaps as\nmany different synapse circuit designs in use as there are brain areas being modeled. This\ndiversity of circuits re\ufb02ects the diversity of the synapse\u2019s computational function. In many\ncomputations, a narrow, square pulse of current is all that is necessary to model the synaptic\ncurrent. In other situations, a longer post-synaptic current pro\ufb01le is desirable to extend the\neffects of extremely short spike durations (e.g., in address-event systems [1],[2], [3], [4]),\nor to create a speci\ufb01c time window of interaction (e.g., for coincidence detection or for\ncreating delays [5]).\n\nTemporal summation or more complex forms of inter-spike interaction are also important\nareas of synaptic design that focus on the response to high-frequency stimulation. Recent\ndesigns for fast-synaptic depression [6], [7], [8] and time-dependent plasticity [9], [10] are\ngood examples of this where some type of memory is used to create interaction between\nincoming spikes. Even simple summation of input current can be very important in address-\nevent systems where a common strategy to reduce hardware is to have a single synapse\ncircuit mimic inputs from many different cells. A very popular design for this purpose\nis the \u201dcurrent-mirror synapse\u201d [4] that is used extensively in its original form or in new\nextended forms [6], [8] to expand the time course of current and to provide summation for\nhigh-frequency spiking. This circuit is simple, compact, and stable, but couples the leak,\npart of the synaptic gain, and the decay \u201dtime-constant\u201d in one control parameter. This is\nrestrictive and often more control is desirable. Alternatively, the same components can be\n\n\farranged to give the user manual-control of the decay to produce a true exponential decay\nwhen operating in the subthreshold region (see Figure 7 (b) of [11]). This circuit, however,\ndoes not provide good summation of multiple synaptic events.\n\nIn this paper we describe a new CMOS synapse circuit, that utilizes current-mode feed-\nback to produce a \ufb01rst-order dynamical system. In the following sections, we describe the\nkinetic model of synaptic conductance, describe the circuit implementation and function,\nprovide a theoretical analysis and \ufb01nally compare our theory against testing results. We\nalso discuss the use of this circuit in various neuromorphic system contexts and conclude\nwith a discussion of the circuit synthesis approach.\n\n2 Proposed synapse model\n\nWe consider a network of spiking neurons, each of which is modeled by the integrate-\nand-\ufb01re model or the slightly more generous Spike Response Model (e.g. [12]). Synaptic\nfunction in such neural networks are often modeled as a time-varying current. The func-\ntional form of this current could be a \u03b4 function, or a limited jump at the time of the spike\nfollowed by an exponential decay. Perhaps the most widely used function in detailed com-\nputational models is the \u03b1-function, a function of the form t\nA more general and practical framework is the neurotransmitter kinetics description pro-\nposed by Destexhe et al. [14]. This approach can synthesize a complete description of\nsynaptic transmission, as well as give an analytic expression for a post-synaptic current in\nsome simpli\ufb01ed schemes. For a two-state ligand-gated channel model, the neurotransmitter\nmolecules, T, are taken to bind to post-synaptic receptors modeled by the \ufb01rst order kinetic\nscheme [15]:\n\n\u03c4 , introduced by [13].\n\nt\n\n\u03c4 e\u2212\n\nR + T\n\n\u03b1\u21c0\u21bd\n\n\u03b2\n\nT R\u2217\n\n(1)\n\nwhere R and T R\u2217 are the unbound and the bound form of the post-synaptic receptor, re-\nspectively. \u03b1 and \u03b2 are the forward and backward rate constants for transmitter binding. In\nthis model, the fraction of bound receptors, r, is described by the equation:\n\ndr\ndt\n\n= \u03b1[T ](1 \u2212 r) \u2212 \u03b2r\n\n(2)\n\nIf the transmitter concentration [T] can be modeled as a short pulse, then r(t) in (2) is a \ufb01rst\norder linear differential equation.\n\nWe propose a synapse model that can be implemented by a CMOS circuit working in the\nsubthreshold region. Our model matches Destexhe et al.\u2019s equations for the time-dependent\nconductance, although we assume a \ufb01xed driving potential.\nIn our synapse model, the\naction potential is modeled as a narrow digital pulse. The pulse width is assumed to be a\n\ufb01xed value tpw, however, in practice tpw may vary slightly from pulse to pulse.\nFigure 1 illustrates the synaptic current response to a single pulse in such a model:\n\n1. A presynaptic spike occurs at tj, during the pulse, the post-synaptic current is\n\nmodeled by:\n\nisyn(t) = isyn(\u221e) + (isyn(tj) \u2212 isyn(\u221e))e\u2212\n\nt\u2212tj\n\n\u03c4r\n\n(3)\n\n2. After the presynaptic pulse terminated at time tj + tpw, the post-synaptic current\n\nis modeled by:\n\nisyn(t) = isyn(tj + tpw)e\u2212\n\nt\u2212tj \u2212tpw\n\n\u03c4d\n\n(4)\n\n\f\u2190 synaptic current\n\n\u2190 presynaptic pulse\ntj+tpw\n\ntj\n\nFigure 1: Synapse model. The action potential (spike) is modeled as a pulse with width\ntpw. The synapse is modeled as \ufb01rst order linear system with synaptic current response\ndescribed by Equations (3) and (4)\n\n3 CMOS circuit synthesis and analysis\n\n3.1 The synthesis approach\n\nLazzaro [11] presents a very simple, compact synapse circuit that has an exponentially-\ndecaying synaptic current after each spike event. The synaptic current always resets to the\nmaximum current value during the spike and is not suitable for the summation of rapid\nbursts of spikes. Another simple and widely used synapse is the current-mirror synapse\nthat has its own set of practical problems related to the coupling of gain, time constant, and\noffset parameters. Our circuit is synthesized from the clean exponential decay from Laz-\nzaro\u2019s synapse and concepts from log domain \ufb01ltering [16], [17] to convert the nonlinear\ncharacteristic of the current mirror synapse into an externally-linear, time-invariant system\n[18].\n\nVdd\n\nM4\n\nM5\n\nspkIn\n\nM1\n\nM2\n\nv\n\nM3\n\nVw\n\ni\n\nvc\n\nC\n\nisyn\n\nM8\n\nM6\n\nV\u03c4\n\nM7\n\nThe pin \u201cisyn\u201d is the synaptic current output.\n\nThe pin \u201cspkIn\u201d receives the spike in-\nFigure 2: The proposed synapse circuit.\nThere\nput with negative logic.\nthe\nare two control parameters.\nsynapse and the input voltage V\u03c4 sets the time constant.\nThe transistors sizes\nare: S1 = 2.4\u00b5m/1.6\u00b5m, S2 = 8\u00b5m/4\u00b5m, S3 = 10\u00b5m/4\u00b5m \u00d7 4, S4 = 4\u00b5m/4\u00b5m,\nS5 = 4\u00b5m/4\u00b5m, S6 = 4\u00b5m/4\u00b5m, S7 = 4\u00b5m/4\u00b5m, S8 = 10\u00b5m/4\u00b5m \u00d7 20. The bod-\nies of NMOS transistors are connected to ground, and the bodies of PMOS transistors are\nconnected to Vdd except for M3.\n\nThe input voltage Vw adjusts the weight of\n\n\f3.2 Basic circuit description\n\nThe synapse circuit consists of eight transistors and one capacitor as shown in Figure 2. All\ntransistors are operated in the subthreshold region. Input voltage spikes are applied through\nan inverter (not shown), onto the gate of the PMOS M1. V\u03c4 sets the current through M7\nthat determines the time constant of the output synaptic current as will be shown later. Vw\ncontrols the magnitude of the synaptic current, so it determines the synaptic weight. The\nvoltage on the capacitor is converted to a current by transistor M6, sent through the current\nmirror M4 \u2212 M5, and into the source follower M3 \u2212 M4. The drain current of M8, a scaled\ncopy of current through M6 produces an inhibitory current. A simple PMOS transistor with\nthe same gate voltage as M5 can provide an excitatory synaptic current.\n\n3.3 Circuit analysis\n\nWe perform an analysis of the circuit by studying its response to a single spike. Assuming a\nlong transistor so that the Early effect can be neglected, the behavior of a NMOS transistor\nworking in the subthreshold region can be described by [19], [20]\n\nids = SI0ne\n\n\u03ban vgs\n\nVT e\n\n(1\u2212\u03ban )vbs\n\nVT\n\n(1 \u2212 e\n\n\u2212vds\nVT )\n\n(5)\n\nwhere VT = KT /q is the thermal voltage, I0n is a positive constant current when Vgs =\nVbs = 0, and S = W\nL is the ratio of the transistor width and length. 0 < \u03ban < 1 is a\nparameter speci\ufb01c to the technology, and we will assume it is constant in this analysis. We\nassume that all transistors are operating in saturation (vds > 4VT ). We also neglect any\nparasitic capacitances.\nThe PMOS source follower M3 \u2212 M4 is used as a level shifter. Detailed discussion on use\nof source followers in the subthreshold region has been discussed in [21]. Combined with\na current mirror M4 \u2212 M5, this sub-circuit implements a logarithmic relationship between\ni and v (as labeled in Figure 2):\n\nv = Vw +\n\nVT\n\u03bap\n\nln(\n\ni\nI0p\n\nS4\n\nS3S5\n\n)\n\n(6)\n\nConsistent with the translinear principle, this logarithmic relationship will make the current\nthrough M2 proportional to 1\ni .\nFor simplicity, we assume a spike begins at time t=0, and the initial voltage on the capacitor\nC is vc(0). The spike ends at time t = tpw. When the spike input is on (0 < t < tpw), the\ndynamics of the circuit for a step input is governed by\n\nC\n\ndvc(t)\n\ndt\n\n=\n\nS2S3S5I 2\nop\nS4S6I0n\n\ne\n\n\u03bap (Vdd\u2212Vw )\n\nVT\n\n\u2212\u03ban vc (t)\n\nVT \u2212 I\u03c4\n\ne\n\nWith the aid of transformation\n\nI\u03c4 = S7Ione\n\n\u03ban V\u03c4\n\nVT\n\nisyn(t) = S8Ione\n\n\u03ban vc(t)\n\nVT\n\nEquation (7) can be changed into a linear ordinary differential equation for isyn(t):\n\ndisyn(t)\n\n+\n\n\u03banI\u03c4\nCVT\n\nS4S6CVT\nIn terms of the general solution expressed in (3), we have\n\ndt\n\nisyn(t) =\n\nS2S3S5S8\u03banI 2\nop\n\n\u03bap (V dd\u2212Vw )\n\nVT\n\ne\n\n\u03c4 =\n\nCVT\n\u03banI\u03c4\n\n(7)\n\n(8)\n\n(9)\n\n(10)\n\n(11)\n\n\fisyn(0) = S8I0ne\nS2S3S5S8I 2\nop\n\nS4S6I\u03c4\n\nisyn(\u221e) =\n\n\u03ban vc (0)\n\nVT\n\n\u03bap (V dd\u2212V w)\n\nVT\n\ne\n\n(12)\n\n(13)\n\nWhen the spike input is off (t > tpw) and we neglect the leakage current from M2, then\nisyn(t) will exponentially decay with the same time constant de\ufb01ned by (11). That is,\n\nisyn(t) = isyn(tpw)e\u2212\n\n(t\u2212tpw )\n\n\u03c4\n\n(14)\n\n4 Results\n\n4.1 Comparison of theory and measurement\n\nWe have fabricated a chip containing the basic synapse circuit as shown in Figure 2 through\nMOSIS in a commercially-available 1.5 \u00b5m, double poly fabrication process.\nIn order\nto compare our theoretical prediction with chip measurement, we \ufb01rst estimate the two\ntransistor parameters \u03ba and I0 by measuring the drain currents from test transistors on the\nsame chip. The current measurements were performed with a Keithley 6517A electrometer.\n\u03ba and I0 are estimated by \ufb01tting Equation (5) (and PMOS with PMOS i-v equation) through\nmultiple measurements of (vgs, ids) points through linear regression. The two parameters\nare found to be \u03ban = 0.67, I0n = 1.32 \u00d7 10\u221214A, \u03bap = 0.77, I0p = 1.33 \u00d7 10\u221219A. In\nestimating these two parameters as well as to compute our model predictions, we estimate\nthe effective transistor width for the wide transistors (e.g. M8 with m=20).\n\n6\n4\n2\n0\n\n)\n\nV\n(\nn\n\nI\nk\np\nS\nv\n\n)\n\nV\n\n(\n \n)\nt\n(\nc\nv\n\n0.4\n\n0\n\n0.5\n\n1\n\n1.5\n\n2\n\n2.5\n\n3\n\n3.5\n\n4\n\nmeasure\ntheory\n\n0.2\n2 x 10\u22127\n\n0\n\n)\n\n0.5\n\n1\n\n1.5\n\n2\n\n2.5\n\n3\n\n3.5\n\n4\n\nA\n\n(\n \n)\nt\n(\nn\ny\ns\n\ni\n\n1\n\n0\n\n0\n\n0.5\n\n1\n\ntheory\nmeasure\n2\n\n1.5\n\ntime (sec)\n\n2.5\n\n3\n\n3.5\n\n4\n\nFigure 3: Comparison between model prediction and measurement. To illustrate the de-\ntailed time course, we used a large spike pulse width. We set V\u03c4 = 0 and Vw = 3.85V .\n\nFigure 3 illustrates our test results compared against the model prediction. We used a very\nwide pulse to exaggerate the details in the time response. Note that as the time constant is\nso large, the isyn(t) rises almost linearly during the spike. In this case, Vw = 3.85V .\n\n4.2 Tuning of synaptic strength and time constant\n\nThe synaptic time constant is solely determined by the leak current through transistor M7.\nThe control is achieved by turning the pin V\u03c4 . The synaptic strength is controlled by Vw\n(which is also coupled with I\u03c4 ) as can be seen from (13). In Figure 4, we present our test\nresults that illustrate how the various time constants and synaptic strengths can be achieved.\n\n\f6\n\n4\n\n2\n\n0\n\n)\n\nV\n\n(\n \n)\nt\n(\nn\nI\nk\np\nS\nv\n\n0\n\n20\n\n40\n\n60\n\n80\n\n0\n\n10\n\n20\n\n30\n\n40\n\n50\n\n6\n\n4\n\n2\n\n0\n\n)\n\nV\n\n(\n \n)\nt\n(\nn\nI\nk\np\nS\nv\n\n)\n\nV\n\n(\n \n)\nt\n(\nc\nv\n\n0.4\n\n0.2\n\nV\u03c4=0.150V\n\nV\u03c4=0.175V\n\nV\u03c4=0.200V\n\n0\n\n0\n4 x 10\u22127\n\n20\n\n40\n\n60\n\n80\n\n)\n\nA\n\n(\n \n)\nt\n(\nn\ny\nS\n\ni\n\n2\n\n0\n\nV\u03c4=0.150V\n\nV\u03c4=0.175V\n\nV\u03c4=0.200V\n\n0\n\n20\n\n40\n\ntime (msec)\n\n60\n\n80\n\n0\n\n)\n\nV\n\n(\n \n)\nt\n(\nc\nv\n\n0.4\n\n0.2\n\n0\n\n3\n\n2\n\n1\n\n0\n\n)\n\nA\n\n(\n \n)\nt\n(\nn\ny\nS\n\ni\n\nVw=3.70V\nVw=3.75V\n\nVw=3.80V\n\n0\nx 10\u22127\n\n10\n\n20\n\n30\n\n40\n\n50\n\nVw=3.70V\n\nVw=3.75V\n\nVw=3.80V\n10\n\n20\n\n30\ntime (msec)\n\n40\n\n50\n\n(a)\n\n(b)\n\nFigure 4: Changing time constant \u03c4 and synaptic strength. (a) Keeping Vw = 3.7V con-\nstant, but changing V\u03c4 . (b) Keeping V\u03c4 = 0.175V , but changing Vw. In both (a) and (b),\nspike pulse width is set as 1 msec.\n\n4.3 Spike train response\n\nThe exponential rise of the synaptic current during a spike naturally provides the summa-\ntion and saturation of incoming spikes. Figure 5 illustrates this behavior in response to an\ninput spike train of \ufb01xed duration.\n\n5 Discussion\n\nWe have proposed a new synapse model and a speci\ufb01c CMOS implementation of the model.\nIn our theoretical analysis, we have ignored all parasitic effects which can play an signi\ufb01-\ncant role in the circuit behavior. For example, as the source follower M3 \u2212 M4 provides the\ngate voltage of M2, switching through M1 will affect the circuit behavior due to parasitic\ncapacitance. We emphasize that various circuit implementation can be designed, especially\na circuit with lower glitch but faster speed is preferred.\n\nThe synaptic model circuit we have described has a single time constant for both its rising\nand decaying phase, whereas the time-course of biological synapses show a faster rising\nphase, but a much slower decaying phase. The second time constant can, in principle, be\nimplemented in our circuit by adding a parallel branch to M7 with some switching circuitry.\nBiological synapses have been best modeled and \ufb01tted by an exponentially-decaying time\ncourse with different time constants for different types of synapse. Our synapse circuit\nmodel captures this important characteristic of the biological synapse, providing an easily\ncontrolled exponential decay and a natural summation and saturation of the synaptic cur-\nrent. By using a simple \ufb01rst order linear model, our synapse circuit model can give the\ncircuit designer an analytically tractable function for use in large, complex, spiking neural\nnetwork system design. The current mirror synapse, in spite of its successful application,\n\n\f)\n\nV\n\n(\n \n)\nt\n(\nc\nv\n\n6\n\n4\n\n2\n\n0\n\n)\n\nV\n\n(\n \n)\nt\n(\nn\nI\nk\np\nS\nv\n\n0.5\n\n0.45\n\n0.4\n\n0.35\n\n0.3\n\n)\n\nA\n\n(\n \n)\nt\n(\nn\ny\nS\n\ni\n\n4\n\n3\n\n2\n\n1\n\n0\n\nx 10\u22128\n\n0\n\n0\n\n0\n\n50\n\n100\n\n150\n\n200\n\n250\n\n50\n\n100\n\n150\n\n200\n\n250\n\n50\n\n100\ntime (msec)\n\n150\n\n200\n\n250\n\nFigure 5: Response to spike train. The spike pulse width is set as 1 msec, and period 15\nmsec. Vw = 3.73V , V\u03c4 = 131mV .\n\nhas been found to be an inconvenient computation unit due to its nonlinearity. Our linear\nsynapse is achieved, however, with the cost of silicon size. This is especially true when\nutilized in an AER system, where the spike can be less than a microsecond. Because our\nlinearity is achieved by employing the CMOS subthreshold current characteristic, working\nwith very narrow pulses will mean the use of large transistor widths to get large charging\ncurrents. We have identi\ufb01ed a number of modi\ufb01cations that may allow the circuit to operate\nat much higher current levels and thus higher speed.\n\n6 Conclusion\n\nWe have identi\ufb01ed a need for more independent control of the synaptic gain, time-\ncourse, and leak parameters in CMOS synapse and have demonstrated a prototype cir-\ncuit that utilizes current-mode feedback to exhibit the same \ufb01rst-order dynamics that are\nutilized by Destexhe et al. [14], [15] to describe a kinetic model description of receptor-\nneurotransmitter binding for a more ef\ufb01cient computational description of the synaptic con-\nductance. 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