{"title": "Neuromorphic Bisable VLSI Synapses with Spike-Timing-Dependent Plasticity", "book": "Advances in Neural Information Processing Systems", "page_first": 1115, "page_last": 1122, "abstract": "", "full_text": "Neuromorphic Bistable VLSI Synapses with\n\nSpike-Timing-Dependent Plasticity\n\nInstitute of Neuroinformatics\n\nUniversity/ETH Zurich\n\nGiacomo Indiveri\n\nCH-8057 Zurich, Switzerland\n\ngiacomo@ini.phys.ethz.ch\n\nAbstract\n\nWe present analog neuromorphic circuits for implementing bistable syn-\napses with spike-timing-dependent plasticity (STDP) properties. In these\ntypes of synapses, the short-term dynamics of the synaptic ef\ufb01cacies are\ngoverned by the relative timing of the pre- and post-synaptic spikes,\nwhile on long time scales the ef\ufb01cacies tend asymptotically to either a\npotentiated state or to a depressed one. We fabricated a prototype VLSI\nchip containing a network of integrate and \ufb01re neurons interconnected\nvia bistable STDP synapses. Test results from this chip demonstrate the\nsynapse\u2019s STDP learning properties, and its long-term bistable charac-\nteristics.\n\n1 Introduction\n\nMost arti\ufb01cial neural network algorithms based on Hebbian learning use correlations of\nmean rate signals to increase the synaptic ef\ufb01cacies between connected neurons. To pre-\nvent uncontrolled growth of synaptic ef\ufb01cacies, these algorithms usually incorporate also\nweight normalization constraints, that are often not biophysically realistic. Recently an\nalternative class of competitive Hebbian learning algorithms has been proposed based on a\nspike-timing-dependent plasticity (STDP) mechanism [1]. It has been argued that the STDP\nmechanism can automatically, and in a biologically plausible way, balance the strengths of\nsynaptic ef\ufb01cacies, thus preserving the bene\ufb01ts of both weight normalization and corre-\nlation based learning rules [16]. In STDP the precise timing of spikes generated by the\nneurons play an important role. If a pre-synaptic spike arrives at the synaptic terminal be-\nfore a post-synaptic spike is emitted, within a critical time window, the synaptic ef\ufb01cacy\nis increased. Conversely if the post-synaptic spike is emitted soon before the pre-synaptic\none arrives, the synaptic ef\ufb01cacy is decreased.\n\nWhile mean rate Hebbian learning algorithms are dif\ufb01cult to implement using analog cir-\ncuits, spike-based learning rules map directly onto VLSI [4, 6, 7]. In this paper we present\ncompact analog circuits that, combined with neuromorphic integrate and \ufb01re (I&F) neurons\nand synaptic circuits with realistic dynamics [8, 12, 11] implement STDP learning for short\ntime scales and asymptotically tend to one of two possible states on long time scales. The\ncircuits required to implement STDP, are described in Section 2. The circuits that imple-\nment bistability are described in Section 3. The network of I&F neurons used to measure\n\n\fthe properties of the bistable STDP synapse is described in Section 4.\n\nLong term storage of synaptic ef\ufb01cacies\n\nThe circuits that drive the synaptic ef\ufb01cacy to one of two possible states on long time scales,\nwere implemented in order to cope with the problem of long term storage of analog values\nin CMOS technology. Conventional VLSI capacitors, the devices typically used as memory\nelements, are not ideal, in that they slowly loose the charge they are supposed to store, due\nto leakage currents. Several solutions have been proposed for long term storage of synaptic\nef\ufb01cacies in analog VLSI neural networks. One of the \ufb01rst suggestions was to use the same\nmethod used for dynamic RAM: to periodically refresh the stored value. This involves\nthough discretization of the analog value to N discrete levels, a method for comparing the\nmeasured voltage to the N levels, and a clocked circuit to periodically refresh the value\non the capacitor. An alternative solution is to use analog-to-digital (ADC) converters, an\noff chip RAM and digital-to-analog converters (DAC), but this approach requires, next\nto a discretization of the value to N states, bulky ADC and DAC circuits. A more recent\nsuggestion is the one of using \ufb02oating gate devices [5]. These devices can store very precise\nanalog values for an inde\ufb01nite amount of time using standard CMOS technology [13], but\nfor spike-based learning rules they would require a control circuit (and thus large area) per\nsynapse. To implement dense arrays of neurons with large numbers of dendritic inputs the\nsynaptic circuits should be as compact as possible.\n\nBistable synapses\n\nAn alternative approach that uses a very small amount of area per synapse is to use bistable\nsynapses. These types of synapses contain minimum feature-size circuits that locally com-\npare the value of the synaptic ef\ufb01cacy stored on the capacitor with a \ufb01xed threshold voltage\nand slowly drive that value either toward a high analog voltage or toward a low one, de-\npending on the output of the comparator (see Section 3).\n\nThe assumption that on long time scales the synaptic ef\ufb01cacy can only assume two values\nis not too severe, for networks of neurons with large numbers of synapses. It has been\nargued that also biological synapses can be indeed discrete on long time-scales. These\nassumptions are compatible with experimental data [3] and are supported by experimental\nevidence [15]. Also from a theoretical perspective it has been shown that the performance\nof associative networks is not necessarily degraded if the dynamic range of the synaptic\nef\ufb01cacy is reduced even to the extreme (two stable states), provided that the transitions\nbetween stable states are stochastic [2].\n\nRelated work\n\nBistable VLSI synapses in networks of I&F neurons have already been proposed in [6], but\nin those circuits, the synaptic ef\ufb01cacy is always clamped to either a high value or a low one,\nalso for short-term dynamics, as opposed to our case, in which the synaptic ef\ufb01cacy can\nassume any analog value between the two. In [7] the authors propose a spike-based learn-\ning circuit, based on a modi\ufb01ed version of Riccati\u2019s equation [10], in which the synaptic\nef\ufb01cacy is a continuous analog voltage; but their synapses require many more transistors\nthan the solution we propose, and do not incorporate long-term bistability. More recently\nBo\ufb01ll and Murray proposed circuits for implementing STDP within a framework of pulse-\nbased neural network circuits [4]. But, next to missing the long-term bistability properties,\ntheir synaptic circuits require digital control signals that cannot be easily generated within\nthe framework of neuromorphic networks of I&F neurons [8, 12].\n\n\fVdd\n\nM3\n\nVtp\n\nM2\nVpot\n\nVdd\n\nM4\n\nM5\n\nVw0\n\nIpot\n\nM6\n\npre\n\nM1\n\nVd\n\nM7\n\nM8\n\nM9\n\nVp\n\nIdep\n\nVdd\n\nM10\n\n/post\n\nCw\n\nVdep\n\nM11\n\nM12\n\nVtd\n\nFigure 1: Synaptic ef\ufb01cacy STDP circuit.\n\n2 The STDP circuits\n\nThe circuit required to implement STDP in a network of I&F neurons is shown in Fig. 1.\nThis circuit increases or decreases the analog voltage Vw0, depending on the relative timing\nof the pulses pre and =post. The voltage Vw0 is then used to set the strength of synaptic\ncircuits with realistic dynamics, of the type described in [11]. The pre- and post-synaptic\npulses pre and =post are generated by compact, low power I&F neurons, of the type de-\nscribed in [9].\n\nThe circuit of Fig. 1 is fully symmetric: upon the arrival of a pre-synaptic pulse pre a\nwaveform Vpot(t) (for potentiating Vw0) is generated. Similarly, upon the arrival of a\npost-synaptic pulse =post, a complementary waveform Vdep(t) (for depotentiating Vw0)\nis generated. Both waveforms have a sharp onset and decay linearly with time, at a rate set\nrespectively by Vtp and Vtd. The pre- and post-synaptic pulses are also used to switch on\ntwo gates (M 8 and M 5), that allow the currents Idep and Ipot to \ufb02ow, as long as the pulses\nare high, either increasing or decreasing the weight. The bias voltages Vp on transistor M 6\nand Vd on M 7 set an upper bound for the maximum amount of current that can be injected\ninto or removed from the capacitor Cw. If transistors M 4(cid:0)M 9 operate in the subthreshold\nregime [13], we can compute the analytical expression of Ipot(t) and Idep(t):\n\nIpot(t) =\n\nIdep(t) =\n\nI0\n\n(cid:20)\nUT\n\ne(cid:0)\n\nVpot(t(cid:0)tpre) + e(cid:0)\n\n(cid:20)\nUT\n\nVp\n\nI0\n\n(cid:20)\nUT\n\ne(cid:0)\n\nVdep(t(cid:0)tpost) + e(cid:0)\n\n(cid:20)\nUT\n\nVd\n\n(1)\n\n(2)\n\nwhere tpre and tpost are the times at which the pre-synaptic and post-synaptic spikes are\nemitted, UT is the thermal voltage, and (cid:20) is the subthreshold slope factor [13]. The change\nin synaptic ef\ufb01cacy is then:\n\n((cid:1)Vw0 = Ipot(tpost)\n\n(cid:1)Vw0 = (cid:0) Idep(tpre)\n\nCp\n\nCd\n\n(cid:1)tspk\n\n(cid:1)tspk\n\nif tpre < tpost\nif tpost < tpre\n\n(3)\n\nwhere (cid:1)tspk is the pre- and post-synaptic spike width, Cp is the parasitic capacitance of\nnode Vpot and Cd the one of node Vdep (not shown in Fig. 1).\nIn Fig. 2(a) we plot experimental data showing how (cid:1)Vw0 changes as a function of (cid:1)t =\ntpre (cid:0) tpost for different values of Vtd and Vtp. Similarly, in Fig. 2(b) we show plots\n\n\f0.5\n\n0\n\n)\n\nV\n\n(\n \n\n0\nw\n\nV\n\n0.5\n\n0\n\n)\n\nV\n\n(\n \n\n0\nw\n\nV\n\n \n\n \n\n\u22120.5\n\n\u221210\n\n\u22125\n\n0\n\n t (ms)\n\n5\n\n10\n\n\u22120.5\n\n\u221210\n\n\u22125\n\n0\n\n t (ms)\n\n5\n\n10\n\n(a)\n\n(b)\n\nFigure 2: Changes in synaptic ef\ufb01cacy, as a function of the difference between pre- and\npost-synaptic spike emission times (cid:1)t = tpre (cid:0)tpost. (a) Curves obtained for four different\nvalues of Vpot (in the left quadrant) and four different values of Vdep (in the right quadrant).\n(b) Typical STDP plot, obtained by setting Vp to 4.0V and Vd to 0.6V.\n\n1.5\n\n)\n\nV\n\n(\n \n\n0\nw\n\nV\n\n0\n0\n5\n\n)\n\nV\n\n(\n \n\np\ne\nd\n\nV\n\n0\n0\n5\n\n0\n0\n\n)\n\nV\n\n(\n \n\ne\nr\np\n\n1\n\n1\n\n1\n\n2\n\n2\n\n3\n\n3\n\n2\n3\n Time (ms)\n\n4\n\n4\n\n4\n\n5\n\n5\n\n5\n\nFigure 3: Changes in Vw0, in response to a sequence of pre-synaptic spikes (top trace). The\nmiddle trace shows how the signal Vdep, triggered by the post-synaptic neuron, decreases\nlinearly with time. The bottom trace shows the series of digital pulses pre, generated with\nevery pre-synaptic spike.\n\nof (cid:1)Vw0 versus (cid:1)t for three different values of Vp and three different values of Vd. As\nthere are four independent control biases, it is possible to set the maximum amplitude and\ntemporal window of in\ufb02uence independently for positive and negative changes in Vw0.\nThe data of Fig. 2 was obtained using a paired-pulse protocol similar to the one used in\nphysiological experiments [14]: one single pair of pre- and post-synaptic spikes was used\nto measure each (cid:1)Vw0 data point, by systematically changing the delay tpre (cid:0) tpost and\nby separating each stimulation session by a few hundreds of milliseconds (to allow the\nsignals to return to their resting steady-state). Unlike the biological experiments, in our\nVLSI setup it is possible to evaluate the effect of multiple pulses on the synaptic ef\ufb01cacy,\nfor very long successive stimulation sessions, monitoring all the internal state variables\nand signals involved in the process. In Fig. 3 we show the effect of multiple pre-synaptic\nspikes, succeeding a post-synaptic one, plotting a trace of the voltage Vw0, together with the\n\nD\nD\nD\nD\n\fVw0\n\nVthr\n\n+\n\nVhigh\n\nM3\n\nVleak\n\nM1\n\nVlow\n\nM4\n\nM5\n\nM6\n\nM2\n\nVw0\n\nFigure 4: Bistability circuit. Depending on Vw0 (cid:0) Vthr, the comparator drives Vw0 to either\nVhigh or Vlow. The rate at which the circuit drives Vw0 toward the asymptote is controlled\nby Vleak and imposed by transistors M 2 and M 4.\n\n\u201cinternal\u201d signal Vdep, generated by the post-synaptic spike, and the pulses pre, generated\nby the per-synaptic neuron. Note how the change in Vw0 is a positive one, when the post-\nsynaptic spike follows a pre-synaptic one, at t = 0:5ms, and is negative when a series\nof pre-synaptic spikes follows the post-synaptic one. The effect of subsequent pre pulses\nfollowing the \ufb01rst post-/pre-synaptic pair is additive, and decreases with time as in Fig. 2.\nAs expected, the anti-causal relationship between pre- and post-synaptic neurons has the\nnet effect of decreasing the synaptic ef\ufb01cacy.\n\n3 The bistability circuit\n\nThe bistability circuit, shown in Fig. 4, drives the voltage Vw0 toward one of two possible\nstates: Vhigh (if Vw0 > Vthr), or Vlow (if Vw0 < Vthr). The signal Vthr is a threshold\nvoltage that can be set externally. The circuit comprises a comparator, and a mixed-mode\nanalog-digital leakage circuit. The comparator is a \ufb01ve transistor transconductance ampli-\n\ufb01er [13] that can be designed using minimum feature-size transistors. The leakage circuit\ncontains two gates that act as digital switches (M 5; M 6) and four transistors that set the\ntwo stable state asymptotes Vhigh and Vlow and that, together with the bias voltage Vleak,\ndetermine the rate at which Vw0 approaches the asymptotes. The bistability circuit drives\nVw0 in two different ways, depending on how large is the distance between the value of Vw0\nitself and the asymptote. If jVw0 (cid:0)Vasj > 4UT the bistability circuit drives Vw0 toward Vas\nlinearly, where Vas represents either Vlow or Vhigh, depending on the sign of (Vw0 (cid:0) Vthr):\n\n(Vw0(t) = Vw0(0) + Ileak\n\nCw\nVw0(t) = Vw0(0) (cid:0) Ileak\nCw\n\nt\nt\n\nif Vw0 > Vthr\nif Vw0 < Vthr\n\n(4)\n\nwhere Cw is the capacitor of Fig. 1 and\n\nIleak = I0e\n\n(cid:20)Vleak (cid:0)Vlow\n\nUT\n\nAs Vw0 gets close to the asymptote and jVw0 (cid:0)Vasj < 4UT , transistors M 2 or M 4 of Fig. 4\ngo out of saturation and Vw0 begins to approach the asymptote exponentially:\n\n(Vw0(t) = Vhigh (cid:0) Vw0(0)e(cid:0)\n\nVw0(t) = Vlow + Vw0(0)e(cid:0)\n\nIleak\nCw UT\n\nt\n\nIleak\nCw UT\n\nt\n\nif Vw0 > Vthr\nif Vw0 < Vthr\n\n(5)\n\nOn long time scales the dynamics of Vw0 are governed by the bistability circuit, while on\nshort time-scales they are governed by the STDP circuits and the precise timing of pre- and\n\n-\n\f3\n\n2.5\n\n)\n\nV\n\n(\n \n\n2\n\n0\nw\n\nV\n\n1.5\n\n1\n0\n\n2\n\n4\n6\n Time (ms)\n\n8\n\n10\n\nFigure 5: Synaptic ef\ufb01cacy bistability. Transition of Vw0 from below threshold to above\nthreshold (Vthr = 1:52V ), with leakage rate set by Vleak = 0:25V and pre- and post-\nsynaptic neurons stimulated in a way to increase Vw0.\n\nI1\n\nI2\n\nM1\n\nM2\n\nO1\n\nO2\n\nFigure 6: Network of leaky I&F neurons with bistable STDP excitatory synapses and in-\nhibitory synapses. The large circles symbolize I&F neurons, the small empty ones bistable\nSTDP excitatory synapses, and the small bars non-plastic inhibitory synapses. The arrows\nin the circles indicate the possibility to inject current from an external source, to stimulate\nthe neurons.\n\npost-synaptic spikes. If the STDP short-term dynamics drive Vw0 above threshold we say\nthat long-term potentiation (LTP) had been induced. And if the short-term dynamics drive\nVw0 below threshold, we say that long-term depression (LTD) has been induced.\nIn Fig. 5 we show how the synaptic ef\ufb01cacy Vw0 changes upon induction of LTP, while\nstimulating the pre- and post-synaptic neurons with uniformly distributed spike trains. The\nasymptote Vlow was set to zero, and Vhigh to 2:75V. The pre- and post-synaptic neurons\nwere injected with constant DC currents in a way to increase Vw0, on average. As shown,\nthe two asymptotes Vlow and Vhigh act as two attractors, or stable equilibrium points,\nwhereas the threshold voltage Vthr acts as an unstable equilibrium point. If the synap-\ntic ef\ufb01cacy is below threshold the short-term dynamics have to \ufb01ght against the long-term\nbistability effect, to increase Vw0. But as soon as Vw0 crosses the threshold, the bistability\ncircuit switches, the effects of the short-term dynamics are reinforced by the asymptotic\ndrive, and Vw0 is quickly driven toward Vhigh.\n\n4 A network of integrate and \ufb01re neurons\n\nThe prototype chip that we used to test the bistable STDP circuits presented in this paper,\ncontains a symmetric network of leaky I&F neurons [9] (see Fig. 6). The experimental data\n\n\f4\n\n)\n\nV\n\n4\n\n)\n\nV\n\n(\n \n\n0\nw\n\nV\n\n(\n \n\n0\nw\n\nV\n\n0\n0\n2\n\n0\n0\n2\n\n0\n0\n\n)\n\nV\n\n(\n \nt\ns\no\np\n\n)\n\nV\n\n(\n \n\ne\nr\np\n\n2\n\n2\n\n2\n\n4\n\n4\n\n6\n\n6\n\n4\n6\n Time (ms)\n\n(a)\n\n8\n\n8\n\n8\n\n10\n\n10\n\n10\n\n0\n0\n2\n\n0\n0\n2\n\n0\n0\n\n)\n\nV\n\n(\n \nt\ns\no\np\n\n)\n\nV\n\n(\n \n\ne\nr\np\n\n2\n\n2\n\n2\n\n8\n\n8\n\n8\n\n10\n\n10\n\n10\n\n4\n\n4\n\n6\n\n6\n\n4\n6\n Time (ms)\n\n(b)\n\nFigure 7: Membrane potentials of pre- and post-synaptic neurons (bottom and middle traces\nrespectively) and synaptic ef\ufb01cacy values (top traces). (a) Changes in Vw0 for low synap-\ntic ef\ufb01cacy values (Vhigh = 2:1V) and no bistability leakage currents (V leak = 0). (b)\nChanges in Vw0 for high synaptic ef\ufb01cacy values (V wh = 3:6V ) and with bistability asymp-\ntotic drive (Vleak = 0:25V).\n\nof Figs. 2, 3, and 5 was obtained by injecting currents in the neurons labeled I1 and O1\nand by measuring the signals from the excitatory synapse on O1. In Fig. 7 we show the\nmembrane potential of I1, O1, and the synaptic ef\ufb01cacy Vw0 of the corresponding synapse,\nin two different conditions. Figure 7(a) shows the changes in Vw0 when both neurons are\nstimulated but no asymptotic drive is used. As shown Vw0 strongly depends on the spike\npatterns of the pre- and post-synaptic neurons. Figure 7(b) shows a scenario in which\nonly neuron I1 is stimulated, but in which the weight Vw0 is close to its high asymptote\n(Vhigh = 3:6V) and in which there is a long-term asymptotic drive (V leak = 0:25). Even\nthough the synaptic weight stays always in its potentiated state, the \ufb01ring rate of O1 is not\nas regular as the one of its efferent neuron. This is mainly due to the small variations of\nVw0 induced by the STDP circuit.\n\n5 Discussion and future work\n\nThe STDP circuits presented here introduce a source of variability in the spike timing of the\nI&F neurons that could be exploited for creating VLSI networks of neurons with stochastic\ndynamics and for implementing spike-based stochastic learning mechanisms [2]. These\nmechanisms rely on the variability of the input signals (e.g. of Poisson distributed spike\ntrains) and on their precise spike-timing in order to induce LTP or LTD only to a small\nspeci\ufb01c sub-set of the synapses stimulated. In future experiments we will characterize the\nproperties of the bistable STDP synapse in response to Poisson distributed spike trains, and\nmeasure transition probabilities as functions of input statistics and circuit parameters.\n\nWe presented compact neuromorphic circuits for implementing bistable STDP synapses in\nVLSI networks of I&F neurons, and showed data from a prototype chip. We demonstrated\nhow these types of synapses can either store their LTP or LTD state for long-term, or switch\nstate depending on the precise timing of the pre- and post-synaptic spikes.\nIn the near\nfuture, we plan to use the simple network of I&F neurons of Fig. 6, present on the prototype\nchip, to analyze the effect of bistable STDP plasticity at a network level. On the long term,\n\n\fwe plan to design a larger chip with these circuits to implement a re-con\ufb01gurable network\nof I&F neurons of O(100) neurons and O(1000) synapses, and use it as a real-time tool for\ninvestigating the computational properties of competitive networks and selective attention\nmodels.\n\nAcknowledgments\n\nI am grateful to Rodney Douglas and Kevan Martin for their support, and to Shih-Chii Liu\nand Stefano Fusi for constructive comments on the manuscript. Some of the ideas that led\nto the design and implementation of the circuits presented were inspired by the Telluride\nWorkshop on Neuromorphic Engineering (http://www.ini.unizh.ch/telluride).\n\nReferences\n\n[1] L. F. Abbott and S. Song. Asymmetric hebbian learning, spike liming and neural response\nvariability. In Advances in Neural Information Processing Systems, volume 11, pages 69\u201375,\n1998.\n\n[2] D. J. Amit and S. Fusi. Dynamic learning in neural networks with material synapses. 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